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ShaderPlayground / deps / luajit / include / lj_asm_x86.h
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1/*
2** x86/x64 IR assembler (SSA IR -> machine code).
3** Copyright (C) 2005-2026 Mike Pall. See Copyright Notice in luajit.h
4*/
5
6/* -- Guard handling ------------------------------------------------------ */
7
8/* Generate an exit stub group at the bottom of the reserved MCode memory. */
9static MCode *asm_exitstub_gen(ASMState *as, ExitNo group)
10{
11 ExitNo i, groupofs = (group*EXITSTUBS_PER_GROUP) & 0xff;
12 MCode *mxp = as->mcbot;
13 MCode *mxpstart = mxp;
14 if (mxp + (2+2)*EXITSTUBS_PER_GROUP+8+5 >= as->mctop)
15 asm_mclimit(as);
16 /* Push low byte of exitno for each exit stub. */
17 *mxp++ = XI_PUSHi8; *mxp++ = (MCode)groupofs;
18 for (i = 1; i < EXITSTUBS_PER_GROUP; i++) {
19 *mxp++ = XI_JMPs; *mxp++ = (MCode)((2+2)*(EXITSTUBS_PER_GROUP - i) - 2);
20 *mxp++ = XI_PUSHi8; *mxp++ = (MCode)(groupofs + i);
21 }
22 /* Push the high byte of the exitno for each exit stub group. */
23 *mxp++ = XI_PUSHi8; *mxp++ = (MCode)((group*EXITSTUBS_PER_GROUP)>>8);
24 /* Store DISPATCH at original stack slot 0. Account for the two push ops. */
25 *mxp++ = XI_MOVmi;
26 *mxp++ = MODRM(XM_OFS8, 0, RID_ESP);
27 *mxp++ = MODRM(XM_SCALE1, RID_ESP, RID_ESP);
28 *mxp++ = 2*sizeof(void *);
29 *(int32_t *)mxp = ptr2addr(J2GG(as->J)->dispatch); mxp += 4;
30 /* Jump to exit handler which fills in the ExitState. */
31 *mxp++ = XI_JMP; mxp += 4;
32 *((int32_t *)(mxp-4)) = jmprel(mxp, (MCode *)(void *)lj_vm_exit_handler);
33 /* Commit the code for this group (even if assembly fails later on). */
34 lj_mcode_commitbot(as->J, mxp);
35 as->mcbot = mxp;
36 as->mclim = as->mcbot + MCLIM_REDZONE;
37 return mxpstart;
38}
39
40/* Setup all needed exit stubs. */
41static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
42{
43 ExitNo i;
44 if (nexits >= EXITSTUBS_PER_GROUP*LJ_MAX_EXITSTUBGR)
45 lj_trace_err(as->J, LJ_TRERR_SNAPOV);
46 for (i = 0; i < (nexits+EXITSTUBS_PER_GROUP-1)/EXITSTUBS_PER_GROUP; i++)
47 if (as->J->exitstubgroup[i] == NULL)
48 as->J->exitstubgroup[i] = asm_exitstub_gen(as, i);
49}
50
51/* Emit conditional branch to exit for guard.
52** It's important to emit this *after* all registers have been allocated,
53** because rematerializations may invalidate the flags.
54*/
55static void asm_guardcc(ASMState *as, int cc)
56{
57 MCode *target = exitstub_addr(as->J, as->snapno);
58 MCode *p = as->mcp;
59 if (LJ_UNLIKELY(p == as->invmcp)) {
60 as->loopinv = 1;
61 *(int32_t *)(p+1) = jmprel(p+5, target);
62 target = p;
63 cc ^= 1;
64 if (as->realign) {
65 emit_sjcc(as, cc, target);
66 return;
67 }
68 }
69 emit_jcc(as, cc, target);
70}
71
72/* -- Memory operand fusion ----------------------------------------------- */
73
74/* Limit linear search to this distance. Avoids O(n^2) behavior. */
75#define CONFLICT_SEARCH_LIM 31
76
77/* Check if a reference is a signed 32 bit constant. */
78static int asm_isk32(ASMState *as, IRRef ref, int32_t *k)
79{
80 if (irref_isk(ref)) {
81 IRIns *ir = IR(ref);
82 if (ir->o != IR_KINT64) {
83 *k = ir->i;
84 return 1;
85 } else if (checki32((int64_t)ir_kint64(ir)->u64)) {
86 *k = (int32_t)ir_kint64(ir)->u64;
87 return 1;
88 }
89 }
90 return 0;
91}
92
93/* Check if there's no conflicting instruction between curins and ref.
94** Also avoid fusing loads if there are multiple references.
95*/
96static int noconflict(ASMState *as, IRRef ref, IROp conflict, int check)
97{
98 IRIns *ir = as->ir;
99 IRRef i = as->curins;
100 if (i > ref + CONFLICT_SEARCH_LIM)
101 return 0; /* Give up, ref is too far away. */
102 while (--i > ref) {
103 if (ir[i].o == conflict)
104 return 0; /* Conflict found. */
105 else if ((check & 1) && ir[i].o == IR_NEWREF)
106 return 0;
107 else if ((check & 2) && (ir[i].op1 == ref || ir[i].op2 == ref))
108 return 0;
109 }
110 return 1; /* Ok, no conflict. */
111}
112
113/* Fuse array base into memory operand. */
114static IRRef asm_fuseabase(ASMState *as, IRRef ref)
115{
116 IRIns *irb = IR(ref);
117 as->mrm.ofs = 0;
118 if (irb->o == IR_FLOAD) {
119 IRIns *ira = IR(irb->op1);
120 lua_assert(irb->op2 == IRFL_TAB_ARRAY);
121 /* We can avoid the FLOAD of t->array for colocated arrays. */
122 if (ira->o == IR_TNEW && ira->op1 <= LJ_MAX_COLOSIZE &&
123 !neverfuse(as) && noconflict(as, irb->op1, IR_NEWREF, 0)) {
124 as->mrm.ofs = (int32_t)sizeof(GCtab); /* Ofs to colocated array. */
125 return irb->op1; /* Table obj. */
126 }
127 } else if (irb->o == IR_ADD && irref_isk(irb->op2)) {
128 /* Fuse base offset (vararg load). */
129 as->mrm.ofs = IR(irb->op2)->i;
130 return irb->op1;
131 }
132 return ref; /* Otherwise use the given array base. */
133}
134
135/* Fuse array reference into memory operand. */
136static void asm_fusearef(ASMState *as, IRIns *ir, RegSet allow)
137{
138 IRIns *irx;
139 lua_assert(ir->o == IR_AREF);
140 as->mrm.base = (uint8_t)ra_alloc1(as, asm_fuseabase(as, ir->op1), allow);
141 irx = IR(ir->op2);
142 if (irref_isk(ir->op2)) {
143 as->mrm.ofs += 8*irx->i;
144 as->mrm.idx = RID_NONE;
145 } else {
146 rset_clear(allow, as->mrm.base);
147 as->mrm.scale = XM_SCALE8;
148 /* Fuse a constant ADD (e.g. t[i+1]) into the offset.
149 ** Doesn't help much without ABCelim, but reduces register pressure.
150 */
151 if (!LJ_64 && /* Has bad effects with negative index on x64. */
152 mayfuse(as, ir->op2) && ra_noreg(irx->r) &&
153 irx->o == IR_ADD && irref_isk(irx->op2)) {
154 as->mrm.ofs += 8*IR(irx->op2)->i;
155 as->mrm.idx = (uint8_t)ra_alloc1(as, irx->op1, allow);
156 } else {
157 as->mrm.idx = (uint8_t)ra_alloc1(as, ir->op2, allow);
158 }
159 }
160}
161
162/* Fuse array/hash/upvalue reference into memory operand.
163** Caveat: this may allocate GPRs for the base/idx registers. Be sure to
164** pass the final allow mask, excluding any GPRs used for other inputs.
165** In particular: 2-operand GPR instructions need to call ra_dest() first!
166*/
167static void asm_fuseahuref(ASMState *as, IRRef ref, RegSet allow)
168{
169 IRIns *ir = IR(ref);
170 if (ra_noreg(ir->r)) {
171 switch ((IROp)ir->o) {
172 case IR_AREF:
173 if (mayfuse(as, ref)) {
174 asm_fusearef(as, ir, allow);
175 return;
176 }
177 break;
178 case IR_HREFK:
179 if (mayfuse(as, ref)) {
180 as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
181 as->mrm.ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
182 as->mrm.idx = RID_NONE;
183 return;
184 }
185 break;
186 case IR_UREFC:
187 if (irref_isk(ir->op1)) {
188 GCfunc *fn = ir_kfunc(IR(ir->op1));
189 GCupval *uv = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv;
190 as->mrm.ofs = ptr2addr(&uv->tv);
191 as->mrm.base = as->mrm.idx = RID_NONE;
192 return;
193 }
194 break;
195 default:
196 lua_assert(ir->o == IR_HREF || ir->o == IR_NEWREF || ir->o == IR_UREFO ||
197 ir->o == IR_KKPTR);
198 break;
199 }
200 }
201 as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
202 as->mrm.ofs = 0;
203 as->mrm.idx = RID_NONE;
204}
205
206/* Fuse FLOAD/FREF reference into memory operand. */
207static void asm_fusefref(ASMState *as, IRIns *ir, RegSet allow)
208{
209 lua_assert(ir->o == IR_FLOAD || ir->o == IR_FREF);
210 as->mrm.ofs = field_ofs[ir->op2];
211 as->mrm.idx = RID_NONE;
212 if (irref_isk(ir->op1)) {
213 as->mrm.ofs += IR(ir->op1)->i;
214 as->mrm.base = RID_NONE;
215 } else {
216 as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
217 }
218}
219
220/* Fuse string reference into memory operand. */
221static void asm_fusestrref(ASMState *as, IRIns *ir, RegSet allow)
222{
223 IRIns *irr;
224 lua_assert(ir->o == IR_STRREF);
225 as->mrm.base = as->mrm.idx = RID_NONE;
226 as->mrm.scale = XM_SCALE1;
227 as->mrm.ofs = sizeof(GCstr);
228 if (irref_isk(ir->op1)) {
229 as->mrm.ofs += IR(ir->op1)->i;
230 } else {
231 Reg r = ra_alloc1(as, ir->op1, allow);
232 rset_clear(allow, r);
233 as->mrm.base = (uint8_t)r;
234 }
235 irr = IR(ir->op2);
236 if (irref_isk(ir->op2)) {
237 as->mrm.ofs += irr->i;
238 } else {
239 Reg r;
240 /* Fuse a constant add into the offset, e.g. string.sub(s, i+10). */
241 if (!LJ_64 && /* Has bad effects with negative index on x64. */
242 mayfuse(as, ir->op2) && irr->o == IR_ADD && irref_isk(irr->op2)) {
243 as->mrm.ofs += IR(irr->op2)->i;
244 r = ra_alloc1(as, irr->op1, allow);
245 } else {
246 r = ra_alloc1(as, ir->op2, allow);
247 }
248 if (as->mrm.base == RID_NONE)
249 as->mrm.base = (uint8_t)r;
250 else
251 as->mrm.idx = (uint8_t)r;
252 }
253}
254
255static void asm_fusexref(ASMState *as, IRRef ref, RegSet allow)
256{
257 IRIns *ir = IR(ref);
258 as->mrm.idx = RID_NONE;
259 if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
260 as->mrm.ofs = ir->i;
261 as->mrm.base = RID_NONE;
262 } else if (ir->o == IR_STRREF) {
263 asm_fusestrref(as, ir, allow);
264 } else {
265 as->mrm.ofs = 0;
266 if (canfuse(as, ir) && ir->o == IR_ADD && ra_noreg(ir->r)) {
267 /* Gather (base+idx*sz)+ofs as emitted by cdata ptr/array indexing. */
268 IRIns *irx;
269 IRRef idx;
270 Reg r;
271 if (asm_isk32(as, ir->op2, &as->mrm.ofs)) { /* Recognize x+ofs. */
272 ref = ir->op1;
273 ir = IR(ref);
274 if (!(ir->o == IR_ADD && canfuse(as, ir) && ra_noreg(ir->r)))
275 goto noadd;
276 }
277 as->mrm.scale = XM_SCALE1;
278 idx = ir->op1;
279 ref = ir->op2;
280 irx = IR(idx);
281 if (!(irx->o == IR_BSHL || irx->o == IR_ADD)) { /* Try other operand. */
282 idx = ir->op2;
283 ref = ir->op1;
284 irx = IR(idx);
285 }
286 if (canfuse(as, irx) && ra_noreg(irx->r)) {
287 if (irx->o == IR_BSHL && irref_isk(irx->op2) && IR(irx->op2)->i <= 3) {
288 /* Recognize idx<<b with b = 0-3, corresponding to sz = (1),2,4,8. */
289 idx = irx->op1;
290 as->mrm.scale = (uint8_t)(IR(irx->op2)->i << 6);
291 } else if (irx->o == IR_ADD && irx->op1 == irx->op2) {
292 /* FOLD does idx*2 ==> idx<<1 ==> idx+idx. */
293 idx = irx->op1;
294 as->mrm.scale = XM_SCALE2;
295 }
296 }
297 r = ra_alloc1(as, idx, allow);
298 rset_clear(allow, r);
299 as->mrm.idx = (uint8_t)r;
300 }
301 noadd:
302 as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
303 }
304}
305
306/* Fuse load into memory operand. */
307static Reg asm_fuseload(ASMState *as, IRRef ref, RegSet allow)
308{
309 IRIns *ir = IR(ref);
310 if (ra_hasreg(ir->r)) {
311 if (allow != RSET_EMPTY) { /* Fast path. */
312 ra_noweak(as, ir->r);
313 return ir->r;
314 }
315 fusespill:
316 /* Force a spill if only memory operands are allowed (asm_x87load). */
317 as->mrm.base = RID_ESP;
318 as->mrm.ofs = ra_spill(as, ir);
319 as->mrm.idx = RID_NONE;
320 return RID_MRM;
321 }
322 if (ir->o == IR_KNUM) {
323 RegSet avail = as->freeset & ~as->modset & RSET_FPR;
324 lua_assert(allow != RSET_EMPTY);
325 if (!(avail & (avail-1))) { /* Fuse if less than two regs available. */
326 as->mrm.ofs = ptr2addr(ir_knum(ir));
327 as->mrm.base = as->mrm.idx = RID_NONE;
328 return RID_MRM;
329 }
330 } else if (ref == REF_BASE || ir->o == IR_KINT64) {
331 RegSet avail = as->freeset & ~as->modset & RSET_GPR;
332 lua_assert(allow != RSET_EMPTY);
333 if (!(avail & (avail-1))) { /* Fuse if less than two regs available. */
334 as->mrm.ofs = ptr2addr(ref == REF_BASE ? (void *)&J2G(as->J)->jit_base : (void *)ir_kint64(ir));
335 as->mrm.base = as->mrm.idx = RID_NONE;
336 return RID_MRM;
337 }
338 } else if (mayfuse(as, ref)) {
339 RegSet xallow = (allow & RSET_GPR) ? allow : RSET_GPR;
340 if (ir->o == IR_SLOAD) {
341 if (!(ir->op2 & (IRSLOAD_PARENT|IRSLOAD_CONVERT)) &&
342 noconflict(as, ref, IR_RETF, 2)) {
343 as->mrm.base = (uint8_t)ra_alloc1(as, REF_BASE, xallow);
344 as->mrm.ofs = 8*((int32_t)ir->op1-1) + ((ir->op2&IRSLOAD_FRAME)?4:0);
345 as->mrm.idx = RID_NONE;
346 return RID_MRM;
347 }
348 } else if (ir->o == IR_FLOAD) {
349 /* Generic fusion is only ok for 32 bit operand (but see asm_comp). */
350 if ((irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t)) &&
351 noconflict(as, ref, IR_FSTORE, 2)) {
352 asm_fusefref(as, ir, xallow);
353 return RID_MRM;
354 }
355 } else if (ir->o == IR_ALOAD || ir->o == IR_HLOAD || ir->o == IR_ULOAD) {
356 if (noconflict(as, ref, ir->o + IRDELTA_L2S, 2+(ir->o != IR_ULOAD))) {
357 asm_fuseahuref(as, ir->op1, xallow);
358 return RID_MRM;
359 }
360 } else if (ir->o == IR_XLOAD) {
361 /* Generic fusion is not ok for 8/16 bit operands (but see asm_comp).
362 ** Fusing unaligned memory operands is ok on x86 (except for SIMD types).
363 */
364 if ((!irt_typerange(ir->t, IRT_I8, IRT_U16)) &&
365 noconflict(as, ref, IR_XSTORE, 2)) {
366 asm_fusexref(as, ir->op1, xallow);
367 return RID_MRM;
368 }
369 } else if (ir->o == IR_VLOAD) {
370 asm_fuseahuref(as, ir->op1, xallow);
371 return RID_MRM;
372 }
373 }
374 if (!(as->freeset & allow) && !emit_canremat(ref) &&
375 (allow == RSET_EMPTY || ra_hasspill(ir->s) || iscrossref(as, ref)))
376 goto fusespill;
377 return ra_allocref(as, ref, allow);
378}
379
380#if LJ_64
381/* Don't fuse a 32 bit load into a 64 bit operation. */
382static Reg asm_fuseloadm(ASMState *as, IRRef ref, RegSet allow, int is64)
383{
384 if (is64 && !irt_is64(IR(ref)->t))
385 return ra_alloc1(as, ref, allow);
386 return asm_fuseload(as, ref, allow);
387}
388#else
389#define asm_fuseloadm(as, ref, allow, is64) asm_fuseload(as, (ref), (allow))
390#endif
391
392/* -- Calls --------------------------------------------------------------- */
393
394/* Count the required number of stack slots for a call. */
395static int asm_count_call_slots(ASMState *as, const CCallInfo *ci, IRRef *args)
396{
397 uint32_t i, nargs = CCI_NARGS(ci);
398 int nslots = 0;
399#if LJ_64
400 if (LJ_ABI_WIN) {
401 nslots = (int)(nargs*2); /* Only matters for more than four args. */
402 } else {
403 int ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
404 for (i = 0; i < nargs; i++)
405 if (args[i] && irt_isfp(IR(args[i])->t)) {
406 if (nfpr > 0) nfpr--; else nslots += 2;
407 } else {
408 if (ngpr > 0) ngpr--; else nslots += 2;
409 }
410 }
411#else
412 int ngpr = 0;
413 if ((ci->flags & CCI_CC_MASK) == CCI_CC_FASTCALL)
414 ngpr = 2;
415 else if ((ci->flags & CCI_CC_MASK) == CCI_CC_THISCALL)
416 ngpr = 1;
417 for (i = 0; i < nargs; i++)
418 if (args[i] && irt_isfp(IR(args[i])->t)) {
419 nslots += irt_isnum(IR(args[i])->t) ? 2 : 1;
420 } else {
421 if (ngpr > 0) ngpr--; else nslots++;
422 }
423#endif
424 return nslots;
425}
426
427/* Generate a call to a C function. */
428static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
429{
430 uint32_t n, nargs = CCI_NARGS(ci);
431 int32_t ofs = STACKARG_OFS;
432#if LJ_64
433 uint32_t gprs = REGARG_GPRS;
434 Reg fpr = REGARG_FIRSTFPR;
435#if !LJ_ABI_WIN
436 MCode *patchnfpr = NULL;
437#endif
438#else
439 uint32_t gprs = 0;
440 if ((ci->flags & CCI_CC_MASK) != CCI_CC_CDECL) {
441 if ((ci->flags & CCI_CC_MASK) == CCI_CC_THISCALL)
442 gprs = (REGARG_GPRS & 31);
443 else if ((ci->flags & CCI_CC_MASK) == CCI_CC_FASTCALL)
444 gprs = REGARG_GPRS;
445 }
446#endif
447 if ((void *)ci->func)
448 emit_call(as, ci->func);
449#if LJ_64
450 if ((ci->flags & CCI_VARARG)) { /* Special handling for vararg calls. */
451#if LJ_ABI_WIN
452 for (n = 0; n < 4 && n < nargs; n++) {
453 IRIns *ir = IR(args[n]);
454 if (irt_isfp(ir->t)) /* Duplicate FPRs in GPRs. */
455 emit_rr(as, XO_MOVDto, (irt_isnum(ir->t) ? REX_64 : 0) | (fpr+n),
456 ((gprs >> (n*5)) & 31)); /* Either MOVD or MOVQ. */
457 }
458#else
459 patchnfpr = --as->mcp; /* Indicate number of used FPRs in register al. */
460 *--as->mcp = XI_MOVrib | RID_EAX;
461#endif
462 }
463#endif
464 for (n = 0; n < nargs; n++) { /* Setup args. */
465 IRRef ref = args[n];
466 IRIns *ir = IR(ref);
467 Reg r;
468#if LJ_64 && LJ_ABI_WIN
469 /* Windows/x64 argument registers are strictly positional. */
470 r = irt_isfp(ir->t) ? (fpr <= REGARG_LASTFPR ? fpr : 0) : (gprs & 31);
471 fpr++; gprs >>= 5;
472#elif LJ_64
473 /* POSIX/x64 argument registers are used in order of appearance. */
474 if (irt_isfp(ir->t)) {
475 r = fpr <= REGARG_LASTFPR ? fpr++ : 0;
476 } else {
477 r = gprs & 31; gprs >>= 5;
478 }
479#else
480 if (ref && irt_isfp(ir->t)) {
481 r = 0;
482 } else {
483 r = gprs & 31; gprs >>= 5;
484 if (!ref) continue;
485 }
486#endif
487 if (r) { /* Argument is in a register. */
488 if (r < RID_MAX_GPR && ref < ASMREF_TMP1) {
489#if LJ_64
490 if (ir->o == IR_KINT64)
491 emit_loadu64(as, r, ir_kint64(ir)->u64);
492 else
493#endif
494 emit_loadi(as, r, ir->i);
495 } else {
496 lua_assert(rset_test(as->freeset, r)); /* Must have been evicted. */
497 if (ra_hasreg(ir->r)) {
498 ra_noweak(as, ir->r);
499 emit_movrr(as, ir, r, ir->r);
500 } else {
501 ra_allocref(as, ref, RID2RSET(r));
502 }
503 }
504 } else if (irt_isfp(ir->t)) { /* FP argument is on stack. */
505 lua_assert(!(irt_isfloat(ir->t) && irref_isk(ref))); /* No float k. */
506 if (LJ_32 && (ofs & 4) && irref_isk(ref)) {
507 /* Split stores for unaligned FP consts. */
508 emit_movmroi(as, RID_ESP, ofs, (int32_t)ir_knum(ir)->u32.lo);
509 emit_movmroi(as, RID_ESP, ofs+4, (int32_t)ir_knum(ir)->u32.hi);
510 } else {
511 r = ra_alloc1(as, ref, RSET_FPR);
512 emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSDto : XO_MOVSSto,
513 r, RID_ESP, ofs);
514 }
515 ofs += (LJ_32 && irt_isfloat(ir->t)) ? 4 : 8;
516 } else { /* Non-FP argument is on stack. */
517 if (LJ_32 && ref < ASMREF_TMP1) {
518 emit_movmroi(as, RID_ESP, ofs, ir->i);
519 } else {
520 r = ra_alloc1(as, ref, RSET_GPR);
521 emit_movtomro(as, REX_64 + r, RID_ESP, ofs);
522 }
523 ofs += sizeof(intptr_t);
524 }
525 checkmclim(as);
526 }
527#if LJ_64 && !LJ_ABI_WIN
528 if (patchnfpr) *patchnfpr = fpr - REGARG_FIRSTFPR;
529#endif
530}
531
532/* Setup result reg/sp for call. Evict scratch regs. */
533static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
534{
535 RegSet drop = RSET_SCRATCH;
536 int hiop = (LJ_32 && (ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t));
537 if ((ci->flags & CCI_NOFPRCLOBBER))
538 drop &= ~RSET_FPR;
539 if (ra_hasreg(ir->r))
540 rset_clear(drop, ir->r); /* Dest reg handled below. */
541 if (hiop && ra_hasreg((ir+1)->r))
542 rset_clear(drop, (ir+1)->r); /* Dest reg handled below. */
543 ra_evictset(as, drop); /* Evictions must be performed first. */
544 if (ra_used(ir)) {
545 if (irt_isfp(ir->t)) {
546 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
547#if LJ_64
548 if ((ci->flags & CCI_CASTU64)) {
549 Reg dest = ir->r;
550 if (ra_hasreg(dest)) {
551 ra_free(as, dest);
552 ra_modified(as, dest);
553 emit_rr(as, XO_MOVD, dest|REX_64, RID_RET); /* Really MOVQ. */
554 }
555 if (ofs) emit_movtomro(as, RID_RET|REX_64, RID_ESP, ofs);
556 } else {
557 ra_destreg(as, ir, RID_FPRET);
558 }
559#else
560 /* Number result is in x87 st0 for x86 calling convention. */
561 Reg dest = ir->r;
562 if (ra_hasreg(dest)) {
563 ra_free(as, dest);
564 ra_modified(as, dest);
565 emit_rmro(as, irt_isnum(ir->t) ? XMM_MOVRM(as) : XO_MOVSS,
566 dest, RID_ESP, ofs);
567 }
568 if ((ci->flags & CCI_CASTU64)) {
569 emit_movtomro(as, RID_RETLO, RID_ESP, ofs);
570 emit_movtomro(as, RID_RETHI, RID_ESP, ofs+4);
571 } else {
572 emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
573 irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
574 }
575#endif
576#if LJ_32
577 } else if (hiop) {
578 ra_destpair(as, ir);
579#endif
580 } else {
581 lua_assert(!irt_ispri(ir->t));
582 ra_destreg(as, ir, RID_RET);
583 }
584 } else if (LJ_32 && irt_isfp(ir->t) && !(ci->flags & CCI_CASTU64)) {
585 emit_x87op(as, XI_FPOP); /* Pop unused result from x87 st0. */
586 }
587}
588
589static void asm_call(ASMState *as, IRIns *ir)
590{
591 IRRef args[CCI_NARGS_MAX];
592 const CCallInfo *ci = &lj_ir_callinfo[ir->op2];
593 asm_collectargs(as, ir, ci, args);
594 asm_setupresult(as, ir, ci);
595 asm_gencall(as, ci, args);
596}
597
598/* Return a constant function pointer or NULL for indirect calls. */
599static void *asm_callx_func(ASMState *as, IRIns *irf, IRRef func)
600{
601#if LJ_32
602 UNUSED(as);
603 if (irref_isk(func))
604 return (void *)irf->i;
605#else
606 if (irref_isk(func)) {
607 MCode *p;
608 if (irf->o == IR_KINT64)
609 p = (MCode *)(void *)ir_k64(irf)->u64;
610 else
611 p = (MCode *)(void *)(uintptr_t)(uint32_t)irf->i;
612 if (p - as->mcp == (int32_t)(p - as->mcp))
613 return p; /* Call target is still in +-2GB range. */
614 /* Avoid the indirect case of emit_call(). Try to hoist func addr. */
615 }
616#endif
617 return NULL;
618}
619
620static void asm_callx(ASMState *as, IRIns *ir)
621{
622 IRRef args[CCI_NARGS_MAX*2];
623 CCallInfo ci;
624 IRRef func;
625 IRIns *irf;
626 int32_t spadj = 0;
627 ci.flags = asm_callx_flags(as, ir);
628 asm_collectargs(as, ir, &ci, args);
629 asm_setupresult(as, ir, &ci);
630#if LJ_32
631 /* Have to readjust stack after non-cdecl calls due to callee cleanup. */
632 if ((ci.flags & CCI_CC_MASK) != CCI_CC_CDECL)
633 spadj = 4 * asm_count_call_slots(as, &ci, args);
634#endif
635 func = ir->op2; irf = IR(func);
636 if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
637 ci.func = (ASMFunction)asm_callx_func(as, irf, func);
638 if (!(void *)ci.func) {
639 /* Use a (hoistable) non-scratch register for indirect calls. */
640 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
641 Reg r = ra_alloc1(as, func, allow);
642 if (LJ_32) emit_spsub(as, spadj); /* Above code may cause restores! */
643 emit_rr(as, XO_GROUP5, XOg_CALL, r);
644 } else if (LJ_32) {
645 emit_spsub(as, spadj);
646 }
647 asm_gencall(as, &ci, args);
648}
649
650/* -- Returns ------------------------------------------------------------- */
651
652/* Return to lower frame. Guard that it goes to the right spot. */
653static void asm_retf(ASMState *as, IRIns *ir)
654{
655 Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
656 void *pc = ir_kptr(IR(ir->op2));
657 int32_t delta = 1+bc_a(*((const BCIns *)pc - 1));
658 as->topslot -= (BCReg)delta;
659 if ((int32_t)as->topslot < 0) as->topslot = 0;
660 irt_setmark(IR(REF_BASE)->t); /* Children must not coalesce with BASE reg. */
661 emit_setgl(as, base, jit_base);
662 emit_addptr(as, base, -8*delta);
663 asm_guardcc(as, CC_NE);
664 emit_gmroi(as, XG_ARITHi(XOg_CMP), base, -4, ptr2addr(pc));
665}
666
667/* -- Type conversions ---------------------------------------------------- */
668
669static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
670{
671 Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
672 Reg dest = ra_dest(as, ir, RSET_GPR);
673 asm_guardcc(as, CC_P);
674 asm_guardcc(as, CC_NE);
675 emit_rr(as, XO_UCOMISD, left, tmp);
676 emit_rr(as, XO_CVTSI2SD, tmp, dest);
677 if (!(as->flags & JIT_F_SPLIT_XMM))
678 emit_rr(as, XO_XORPS, tmp, tmp); /* Avoid partial register stall. */
679 checkmclim(as);
680 emit_rr(as, XO_CVTTSD2SI, dest, left);
681 /* Can't fuse since left is needed twice. */
682}
683
684static void asm_tobit(ASMState *as, IRIns *ir)
685{
686 Reg dest = ra_dest(as, ir, RSET_GPR);
687 Reg tmp = ra_noreg(IR(ir->op1)->r) ?
688 ra_alloc1(as, ir->op1, RSET_FPR) :
689 ra_scratch(as, RSET_FPR);
690 Reg right = asm_fuseload(as, ir->op2, rset_exclude(RSET_FPR, tmp));
691 emit_rr(as, XO_MOVDto, tmp, dest);
692 emit_mrm(as, XO_ADDSD, tmp, right);
693 ra_left(as, tmp, ir->op1);
694}
695
696static void asm_conv(ASMState *as, IRIns *ir)
697{
698 IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
699 int st64 = (st == IRT_I64 || st == IRT_U64 || (LJ_64 && st == IRT_P64));
700 int stfp = (st == IRT_NUM || st == IRT_FLOAT);
701 IRRef lref = ir->op1;
702 lua_assert(irt_type(ir->t) != st);
703 lua_assert(!(LJ_32 && (irt_isint64(ir->t) || st64))); /* Handled by SPLIT. */
704 if (irt_isfp(ir->t)) {
705 Reg dest = ra_dest(as, ir, RSET_FPR);
706 if (stfp) { /* FP to FP conversion. */
707 Reg left = asm_fuseload(as, lref, RSET_FPR);
708 emit_mrm(as, st == IRT_NUM ? XO_CVTSD2SS : XO_CVTSS2SD, dest, left);
709 if (left == dest) return; /* Avoid the XO_XORPS. */
710 } else if (LJ_32 && st == IRT_U32) { /* U32 to FP conversion on x86. */
711 /* number = (2^52+2^51 .. u32) - (2^52+2^51) */
712 cTValue *k = lj_ir_k64_find(as->J, U64x(43380000,00000000));
713 Reg bias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
714 if (irt_isfloat(ir->t))
715 emit_rr(as, XO_CVTSD2SS, dest, dest);
716 emit_rr(as, XO_SUBSD, dest, bias); /* Subtract 2^52+2^51 bias. */
717 emit_rr(as, XO_XORPS, dest, bias); /* Merge bias and integer. */
718 emit_loadn(as, bias, k);
719 checkmclim(as);
720 emit_mrm(as, XO_MOVD, dest, asm_fuseload(as, lref, RSET_GPR));
721 return;
722 } else { /* Integer to FP conversion. */
723 Reg left = (LJ_64 && (st == IRT_U32 || st == IRT_U64)) ?
724 ra_alloc1(as, lref, RSET_GPR) :
725 asm_fuseloadm(as, lref, RSET_GPR, st64);
726 if (LJ_64 && st == IRT_U64) {
727 MCLabel l_end = emit_label(as);
728 const void *k = lj_ir_k64_find(as->J, U64x(43f00000,00000000));
729 emit_rma(as, XO_ADDSD, dest, k); /* Add 2^64 to compensate. */
730 emit_sjcc(as, CC_NS, l_end);
731 emit_rr(as, XO_TEST, left|REX_64, left); /* Check if u64 >= 2^63. */
732 }
733 emit_mrm(as, irt_isnum(ir->t) ? XO_CVTSI2SD : XO_CVTSI2SS,
734 dest|((LJ_64 && (st64 || st == IRT_U32)) ? REX_64 : 0), left);
735 }
736 if (!(as->flags & JIT_F_SPLIT_XMM))
737 emit_rr(as, XO_XORPS, dest, dest); /* Avoid partial register stall. */
738 } else if (stfp) { /* FP to integer conversion. */
739 if (irt_isguard(ir->t)) {
740 /* Checked conversions are only supported from number to int. */
741 lua_assert(irt_isint(ir->t) && st == IRT_NUM);
742 asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
743 } else {
744 Reg dest = ra_dest(as, ir, RSET_GPR);
745 x86Op op = st == IRT_NUM ?
746 ((ir->op2 & IRCONV_TRUNC) ? XO_CVTTSD2SI : XO_CVTSD2SI) :
747 ((ir->op2 & IRCONV_TRUNC) ? XO_CVTTSS2SI : XO_CVTSS2SI);
748 if (LJ_64 ? irt_isu64(ir->t) : irt_isu32(ir->t)) {
749 /* LJ_64: For inputs >= 2^63 add -2^64, convert again. */
750 /* LJ_32: For inputs >= 2^31 add -2^31, convert again and add 2^31. */
751 Reg tmp = ra_noreg(IR(lref)->r) ? ra_alloc1(as, lref, RSET_FPR) :
752 ra_scratch(as, RSET_FPR);
753 MCLabel l_end = emit_label(as);
754 if (LJ_32)
755 emit_gri(as, XG_ARITHi(XOg_ADD), dest, (int32_t)0x80000000);
756 emit_rr(as, op, dest|REX_64, tmp);
757 if (st == IRT_NUM)
758 emit_rma(as, XO_ADDSD, tmp, lj_ir_k64_find(as->J,
759 LJ_64 ? U64x(c3f00000,00000000) : U64x(c1e00000,00000000)));
760 else
761 emit_rma(as, XO_ADDSS, tmp, lj_ir_k64_find(as->J,
762 LJ_64 ? U64x(00000000,df800000) : U64x(00000000,cf000000)));
763 emit_sjcc(as, CC_NS, l_end);
764 emit_rr(as, XO_TEST, dest|REX_64, dest); /* Check if dest negative. */
765 emit_rr(as, op, dest|REX_64, tmp);
766 ra_left(as, tmp, lref);
767 } else {
768 Reg left = asm_fuseload(as, lref, RSET_FPR);
769 if (LJ_64 && irt_isu32(ir->t))
770 emit_rr(as, XO_MOV, dest, dest); /* Zero hiword. */
771 emit_mrm(as, op,
772 dest|((LJ_64 &&
773 (irt_is64(ir->t) || irt_isu32(ir->t))) ? REX_64 : 0),
774 left);
775 }
776 }
777 } else if (st >= IRT_I8 && st <= IRT_U16) { /* Extend to 32 bit integer. */
778 Reg left, dest = ra_dest(as, ir, RSET_GPR);
779 RegSet allow = RSET_GPR;
780 x86Op op;
781 lua_assert(irt_isint(ir->t) || irt_isu32(ir->t));
782 if (st == IRT_I8) {
783 op = XO_MOVSXb; allow = RSET_GPR8; dest |= FORCE_REX;
784 } else if (st == IRT_U8) {
785 op = XO_MOVZXb; allow = RSET_GPR8; dest |= FORCE_REX;
786 } else if (st == IRT_I16) {
787 op = XO_MOVSXw;
788 } else {
789 op = XO_MOVZXw;
790 }
791 left = asm_fuseload(as, lref, allow);
792 /* Add extra MOV if source is already in wrong register. */
793 if (!LJ_64 && left != RID_MRM && !rset_test(allow, left)) {
794 Reg tmp = ra_scratch(as, allow);
795 emit_rr(as, op, dest, tmp);
796 emit_rr(as, XO_MOV, tmp, left);
797 } else {
798 emit_mrm(as, op, dest, left);
799 }
800 } else { /* 32/64 bit integer conversions. */
801 if (LJ_32) { /* Only need to handle 32/32 bit no-op (cast) on x86. */
802 Reg dest = ra_dest(as, ir, RSET_GPR);
803 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
804 } else if (irt_is64(ir->t)) {
805 Reg dest = ra_dest(as, ir, RSET_GPR);
806 if (st64 || !(ir->op2 & IRCONV_SEXT)) {
807 /* 64/64 bit no-op (cast) or 32 to 64 bit zero extension. */
808 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
809 } else { /* 32 to 64 bit sign extension. */
810 Reg left = asm_fuseload(as, lref, RSET_GPR);
811 emit_mrm(as, XO_MOVSXd, dest|REX_64, left);
812 }
813 } else {
814 Reg dest = ra_dest(as, ir, RSET_GPR);
815 if (st64) {
816 Reg left = asm_fuseload(as, lref, RSET_GPR);
817 /* This is either a 32 bit reg/reg mov which zeroes the hiword
818 ** or a load of the loword from a 64 bit address.
819 */
820 emit_mrm(as, XO_MOV, dest, left);
821 } else { /* 32/32 bit no-op (cast). */
822 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
823 }
824 }
825 }
826}
827
828#if LJ_32 && LJ_HASFFI
829/* No SSE conversions to/from 64 bit on x86, so resort to ugly x87 code. */
830
831/* 64 bit integer to FP conversion in 32 bit mode. */
832static void asm_conv_fp_int64(ASMState *as, IRIns *ir)
833{
834 Reg hi = ra_alloc1(as, ir->op1, RSET_GPR);
835 Reg lo = ra_alloc1(as, (ir-1)->op1, rset_exclude(RSET_GPR, hi));
836 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
837 Reg dest = ir->r;
838 if (ra_hasreg(dest)) {
839 ra_free(as, dest);
840 ra_modified(as, dest);
841 emit_rmro(as, irt_isnum(ir->t) ? XMM_MOVRM(as) : XO_MOVSS,
842 dest, RID_ESP, ofs);
843 }
844 emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
845 irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
846 if (((ir-1)->op2 & IRCONV_SRCMASK) == IRT_U64) {
847 /* For inputs in [2^63,2^64-1] add 2^64 to compensate. */
848 MCLabel l_end = emit_label(as);
849 emit_rma(as, XO_FADDq, XOg_FADDq,
850 lj_ir_k64_find(as->J, U64x(43f00000,00000000)));
851 emit_sjcc(as, CC_NS, l_end);
852 emit_rr(as, XO_TEST, hi, hi); /* Check if u64 >= 2^63. */
853 } else {
854 lua_assert(((ir-1)->op2 & IRCONV_SRCMASK) == IRT_I64);
855 }
856 emit_rmro(as, XO_FILDq, XOg_FILDq, RID_ESP, 0);
857 /* NYI: Avoid narrow-to-wide store-to-load forwarding stall. */
858 emit_rmro(as, XO_MOVto, hi, RID_ESP, 4);
859 emit_rmro(as, XO_MOVto, lo, RID_ESP, 0);
860}
861
862/* FP to 64 bit integer conversion in 32 bit mode. */
863static void asm_conv_int64_fp(ASMState *as, IRIns *ir)
864{
865 IRType st = (IRType)((ir-1)->op2 & IRCONV_SRCMASK);
866 IRType dt = (((ir-1)->op2 & IRCONV_DSTMASK) >> IRCONV_DSH);
867 Reg lo, hi;
868 lua_assert(st == IRT_NUM || st == IRT_FLOAT);
869 lua_assert(dt == IRT_I64 || dt == IRT_U64);
870 lua_assert(((ir-1)->op2 & IRCONV_TRUNC));
871 hi = ra_dest(as, ir, RSET_GPR);
872 lo = ra_dest(as, ir-1, rset_exclude(RSET_GPR, hi));
873 if (ra_used(ir-1)) emit_rmro(as, XO_MOV, lo, RID_ESP, 0);
874 /* NYI: Avoid wide-to-narrow store-to-load forwarding stall. */
875 if (!(as->flags & JIT_F_SSE3)) { /* Set FPU rounding mode to default. */
876 emit_rmro(as, XO_FLDCW, XOg_FLDCW, RID_ESP, 4);
877 emit_rmro(as, XO_MOVto, lo, RID_ESP, 4);
878 emit_gri(as, XG_ARITHi(XOg_AND), lo, 0xf3ff);
879 }
880 if (dt == IRT_U64) {
881 /* For inputs in [2^63,2^64-1] add -2^64 and convert again. */
882 MCLabel l_pop, l_end = emit_label(as);
883 emit_x87op(as, XI_FPOP);
884 l_pop = emit_label(as);
885 emit_sjmp(as, l_end);
886 emit_rmro(as, XO_MOV, hi, RID_ESP, 4);
887 if ((as->flags & JIT_F_SSE3))
888 emit_rmro(as, XO_FISTTPq, XOg_FISTTPq, RID_ESP, 0);
889 else
890 emit_rmro(as, XO_FISTPq, XOg_FISTPq, RID_ESP, 0);
891 emit_rma(as, XO_FADDq, XOg_FADDq,
892 lj_ir_k64_find(as->J, U64x(c3f00000,00000000)));
893 emit_sjcc(as, CC_NS, l_pop);
894 emit_rr(as, XO_TEST, hi, hi); /* Check if out-of-range (2^63). */
895 }
896 emit_rmro(as, XO_MOV, hi, RID_ESP, 4);
897 if ((as->flags & JIT_F_SSE3)) { /* Truncation is easy with SSE3. */
898 emit_rmro(as, XO_FISTTPq, XOg_FISTTPq, RID_ESP, 0);
899 } else { /* Otherwise set FPU rounding mode to truncate before the store. */
900 emit_rmro(as, XO_FISTPq, XOg_FISTPq, RID_ESP, 0);
901 emit_rmro(as, XO_FLDCW, XOg_FLDCW, RID_ESP, 0);
902 emit_rmro(as, XO_MOVtow, lo, RID_ESP, 0);
903 emit_rmro(as, XO_ARITHw(XOg_OR), lo, RID_ESP, 0);
904 emit_loadi(as, lo, 0xc00);
905 emit_rmro(as, XO_FNSTCW, XOg_FNSTCW, RID_ESP, 0);
906 }
907 if (dt == IRT_U64)
908 emit_x87op(as, XI_FDUP);
909 emit_mrm(as, st == IRT_NUM ? XO_FLDq : XO_FLDd,
910 st == IRT_NUM ? XOg_FLDq: XOg_FLDd,
911 asm_fuseload(as, ir->op1, RSET_EMPTY));
912}
913#endif
914
915static void asm_strto(ASMState *as, IRIns *ir)
916{
917 /* Force a spill slot for the destination register (if any). */
918 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
919 IRRef args[2];
920 RegSet drop = RSET_SCRATCH;
921 if ((drop & RSET_FPR) != RSET_FPR && ra_hasreg(ir->r))
922 rset_set(drop, ir->r); /* WIN64 doesn't spill all FPRs. */
923 ra_evictset(as, drop);
924 asm_guardcc(as, CC_E);
925 emit_rr(as, XO_TEST, RID_RET, RID_RET); /* Test return status. */
926 args[0] = ir->op1; /* GCstr *str */
927 args[1] = ASMREF_TMP1; /* TValue *n */
928 asm_gencall(as, ci, args);
929 /* Store the result to the spill slot or temp slots. */
930 emit_rmro(as, XO_LEA, ra_releasetmp(as, ASMREF_TMP1)|REX_64,
931 RID_ESP, sps_scale(ir->s));
932}
933
934static void asm_tostr(ASMState *as, IRIns *ir)
935{
936 IRIns *irl = IR(ir->op1);
937 IRRef args[2];
938 args[0] = ASMREF_L;
939 as->gcsteps++;
940 if (irt_isnum(irl->t)) {
941 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_str_fromnum];
942 args[1] = ASMREF_TMP1; /* const lua_Number * */
943 asm_setupresult(as, ir, ci); /* GCstr * */
944 asm_gencall(as, ci, args);
945 emit_rmro(as, XO_LEA, ra_releasetmp(as, ASMREF_TMP1)|REX_64,
946 RID_ESP, ra_spill(as, irl));
947 } else {
948 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_str_fromint];
949 args[1] = ir->op1; /* int32_t k */
950 asm_setupresult(as, ir, ci); /* GCstr * */
951 asm_gencall(as, ci, args);
952 }
953}
954
955/* -- Memory references --------------------------------------------------- */
956
957static void asm_aref(ASMState *as, IRIns *ir)
958{
959 Reg dest = ra_dest(as, ir, RSET_GPR);
960 asm_fusearef(as, ir, RSET_GPR);
961 if (!(as->mrm.idx == RID_NONE && as->mrm.ofs == 0))
962 emit_mrm(as, XO_LEA, dest, RID_MRM);
963 else if (as->mrm.base != dest)
964 emit_rr(as, XO_MOV, dest, as->mrm.base);
965}
966
967/* Merge NE(HREF, niltv) check. */
968static MCode *merge_href_niltv(ASMState *as, IRIns *ir)
969{
970 /* Assumes nothing else generates NE of HREF. */
971 if ((ir[1].o == IR_NE || ir[1].o == IR_EQ) && ir[1].op1 == as->curins &&
972 ra_hasreg(ir->r)) {
973 MCode *p = as->mcp;
974 p += (LJ_64 && *p != XI_ARITHi) ? 7+6 : 6+6;
975 /* Ensure no loop branch inversion happened. */
976 if (p[-6] == 0x0f && p[-5] == XI_JCCn+(CC_NE^(ir[1].o & 1))) {
977 as->mcp = p; /* Kill cmp reg, imm32 + jz exit. */
978 return p + *(int32_t *)(p-4); /* Return exit address. */
979 }
980 }
981 return NULL;
982}
983
984/* Inlined hash lookup. Specialized for key type and for const keys.
985** The equivalent C code is:
986** Node *n = hashkey(t, key);
987** do {
988** if (lj_obj_equal(&n->key, key)) return &n->val;
989** } while ((n = nextnode(n)));
990** return niltv(L);
991*/
992static void asm_href(ASMState *as, IRIns *ir)
993{
994 MCode *nilexit = merge_href_niltv(as, ir); /* Do this before any restores. */
995 RegSet allow = RSET_GPR;
996 Reg dest = ra_dest(as, ir, allow);
997 Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
998 Reg key = RID_NONE, tmp = RID_NONE;
999 IRIns *irkey = IR(ir->op2);
1000 int isk = irref_isk(ir->op2);
1001 IRType1 kt = irkey->t;
1002 uint32_t khash;
1003 MCLabel l_end, l_loop, l_next;
1004
1005 if (!isk) {
1006 rset_clear(allow, tab);
1007 key = ra_alloc1(as, ir->op2, irt_isnum(kt) ? RSET_FPR : allow);
1008 if (!irt_isstr(kt))
1009 tmp = ra_scratch(as, rset_exclude(allow, key));
1010 }
1011
1012 /* Key not found in chain: jump to exit (if merged with NE) or load niltv. */
1013 l_end = emit_label(as);
1014 if (nilexit && ir[1].o == IR_NE) {
1015 emit_jcc(as, CC_E, nilexit); /* XI_JMP is not found by lj_asm_patchexit. */
1016 nilexit = NULL;
1017 } else {
1018 emit_loada(as, dest, niltvg(J2G(as->J)));
1019 }
1020
1021 /* Follow hash chain until the end. */
1022 l_loop = emit_sjcc_label(as, CC_NZ);
1023 emit_rr(as, XO_TEST, dest, dest);
1024 emit_rmro(as, XO_MOV, dest, dest, offsetof(Node, next));
1025 l_next = emit_label(as);
1026
1027 /* Type and value comparison. */
1028 if (nilexit)
1029 emit_jcc(as, CC_E, nilexit);
1030 else
1031 emit_sjcc(as, CC_E, l_end);
1032 checkmclim(as);
1033 if (irt_isnum(kt)) {
1034 if (isk) {
1035 /* Assumes -0.0 is already canonicalized to +0.0. */
1036 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.lo),
1037 (int32_t)ir_knum(irkey)->u32.lo);
1038 emit_sjcc(as, CC_NE, l_next);
1039 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.hi),
1040 (int32_t)ir_knum(irkey)->u32.hi);
1041 } else {
1042 emit_sjcc(as, CC_P, l_next);
1043 emit_rmro(as, XO_UCOMISD, key, dest, offsetof(Node, key.n));
1044 emit_sjcc(as, CC_AE, l_next);
1045 /* The type check avoids NaN penalties and complaints from Valgrind. */
1046#if LJ_64
1047 emit_u32(as, LJ_TISNUM);
1048 emit_rmro(as, XO_ARITHi, XOg_CMP, dest, offsetof(Node, key.it));
1049#else
1050 emit_i8(as, LJ_TISNUM);
1051 emit_rmro(as, XO_ARITHi8, XOg_CMP, dest, offsetof(Node, key.it));
1052#endif
1053 }
1054#if LJ_64
1055 } else if (irt_islightud(kt)) {
1056 emit_rmro(as, XO_CMP, key|REX_64, dest, offsetof(Node, key.u64));
1057#endif
1058 } else {
1059 if (!irt_ispri(kt)) {
1060 lua_assert(irt_isaddr(kt));
1061 if (isk)
1062 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.gcr),
1063 ptr2addr(ir_kgc(irkey)));
1064 else
1065 emit_rmro(as, XO_CMP, key, dest, offsetof(Node, key.gcr));
1066 emit_sjcc(as, CC_NE, l_next);
1067 }
1068 lua_assert(!irt_isnil(kt));
1069 emit_i8(as, irt_toitype(kt));
1070 emit_rmro(as, XO_ARITHi8, XOg_CMP, dest, offsetof(Node, key.it));
1071 }
1072 emit_sfixup(as, l_loop);
1073
1074 /* Load main position relative to tab->node into dest. */
1075 khash = isk ? ir_khash(irkey) : 1;
1076 if (khash == 0) {
1077 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, node));
1078 } else {
1079 emit_rmro(as, XO_ARITH(XOg_ADD), dest, tab, offsetof(GCtab, node));
1080 if ((as->flags & JIT_F_PREFER_IMUL)) {
1081 emit_i8(as, sizeof(Node));
1082 emit_rr(as, XO_IMULi8, dest, dest);
1083 } else {
1084 emit_shifti(as, XOg_SHL, dest, 3);
1085 emit_rmrxo(as, XO_LEA, dest, dest, dest, XM_SCALE2, 0);
1086 }
1087 if (isk) {
1088 emit_gri(as, XG_ARITHi(XOg_AND), dest, (int32_t)khash);
1089 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, hmask));
1090 } else if (irt_isstr(kt)) {
1091 emit_rmro(as, XO_ARITH(XOg_AND), dest, key, offsetof(GCstr, hash));
1092 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, hmask));
1093 } else { /* Must match with hashrot() in lj_tab.c. */
1094 emit_rmro(as, XO_ARITH(XOg_AND), dest, tab, offsetof(GCtab, hmask));
1095 emit_rr(as, XO_ARITH(XOg_SUB), dest, tmp);
1096 emit_shifti(as, XOg_ROL, tmp, HASH_ROT3);
1097 emit_rr(as, XO_ARITH(XOg_XOR), dest, tmp);
1098 checkmclim(as);
1099 emit_shifti(as, XOg_ROL, dest, HASH_ROT2);
1100 emit_rr(as, XO_ARITH(XOg_SUB), tmp, dest);
1101 emit_shifti(as, XOg_ROL, dest, HASH_ROT1);
1102 emit_rr(as, XO_ARITH(XOg_XOR), tmp, dest);
1103 if (irt_isnum(kt)) {
1104 emit_rr(as, XO_ARITH(XOg_ADD), dest, dest);
1105#if LJ_64
1106 emit_shifti(as, XOg_SHR|REX_64, dest, 32);
1107 emit_rr(as, XO_MOV, tmp, dest);
1108 emit_rr(as, XO_MOVDto, key|REX_64, dest);
1109#else
1110 emit_rmro(as, XO_MOV, dest, RID_ESP, ra_spill(as, irkey)+4);
1111 emit_rr(as, XO_MOVDto, key, tmp);
1112#endif
1113 } else {
1114 emit_rr(as, XO_MOV, tmp, key);
1115 emit_rmro(as, XO_LEA, dest, key, HASH_BIAS);
1116 }
1117 }
1118 }
1119}
1120
1121static void asm_hrefk(ASMState *as, IRIns *ir)
1122{
1123 IRIns *kslot = IR(ir->op2);
1124 IRIns *irkey = IR(kslot->op1);
1125 int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
1126 Reg dest = ra_used(ir) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
1127 Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
1128#if !LJ_64
1129 MCLabel l_exit;
1130#endif
1131 lua_assert(ofs % sizeof(Node) == 0);
1132 if (ra_hasreg(dest)) {
1133 if (ofs != 0) {
1134 if (dest == node && !(as->flags & JIT_F_LEA_AGU))
1135 emit_gri(as, XG_ARITHi(XOg_ADD), dest, ofs);
1136 else
1137 emit_rmro(as, XO_LEA, dest, node, ofs);
1138 } else if (dest != node) {
1139 emit_rr(as, XO_MOV, dest, node);
1140 }
1141 }
1142 asm_guardcc(as, CC_NE);
1143#if LJ_64
1144 if (!irt_ispri(irkey->t)) {
1145 Reg key = ra_scratch(as, rset_exclude(RSET_GPR, node));
1146 emit_rmro(as, XO_CMP, key|REX_64, node,
1147 ofs + (int32_t)offsetof(Node, key.u64));
1148 lua_assert(irt_isnum(irkey->t) || irt_isgcv(irkey->t));
1149 /* Assumes -0.0 is already canonicalized to +0.0. */
1150 emit_loadu64(as, key, irt_isnum(irkey->t) ? ir_knum(irkey)->u64 :
1151 ((uint64_t)irt_toitype(irkey->t) << 32) |
1152 (uint64_t)(uint32_t)ptr2addr(ir_kgc(irkey)));
1153 } else {
1154 lua_assert(!irt_isnil(irkey->t));
1155 emit_i8(as, irt_toitype(irkey->t));
1156 emit_rmro(as, XO_ARITHi8, XOg_CMP, node,
1157 ofs + (int32_t)offsetof(Node, key.it));
1158 }
1159#else
1160 l_exit = emit_label(as);
1161 if (irt_isnum(irkey->t)) {
1162 /* Assumes -0.0 is already canonicalized to +0.0. */
1163 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
1164 ofs + (int32_t)offsetof(Node, key.u32.lo),
1165 (int32_t)ir_knum(irkey)->u32.lo);
1166 emit_sjcc(as, CC_NE, l_exit);
1167 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
1168 ofs + (int32_t)offsetof(Node, key.u32.hi),
1169 (int32_t)ir_knum(irkey)->u32.hi);
1170 } else {
1171 if (!irt_ispri(irkey->t)) {
1172 lua_assert(irt_isgcv(irkey->t));
1173 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
1174 ofs + (int32_t)offsetof(Node, key.gcr),
1175 ptr2addr(ir_kgc(irkey)));
1176 emit_sjcc(as, CC_NE, l_exit);
1177 }
1178 lua_assert(!irt_isnil(irkey->t));
1179 emit_i8(as, irt_toitype(irkey->t));
1180 emit_rmro(as, XO_ARITHi8, XOg_CMP, node,
1181 ofs + (int32_t)offsetof(Node, key.it));
1182 }
1183#endif
1184}
1185
1186static void asm_newref(ASMState *as, IRIns *ir)
1187{
1188 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_tab_newkey];
1189 IRRef args[3];
1190 IRIns *irkey;
1191 Reg tmp;
1192 if (ir->r == RID_SINK)
1193 return;
1194 args[0] = ASMREF_L; /* lua_State *L */
1195 args[1] = ir->op1; /* GCtab *t */
1196 args[2] = ASMREF_TMP1; /* cTValue *key */
1197 asm_setupresult(as, ir, ci); /* TValue * */
1198 asm_gencall(as, ci, args);
1199 tmp = ra_releasetmp(as, ASMREF_TMP1);
1200 irkey = IR(ir->op2);
1201 if (irt_isnum(irkey->t)) {
1202 /* For numbers use the constant itself or a spill slot as a TValue. */
1203 if (irref_isk(ir->op2))
1204 emit_loada(as, tmp, ir_knum(irkey));
1205 else
1206 emit_rmro(as, XO_LEA, tmp|REX_64, RID_ESP, ra_spill(as, irkey));
1207 } else {
1208 /* Otherwise use g->tmptv to hold the TValue. */
1209 if (!irref_isk(ir->op2)) {
1210 Reg src = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, tmp));
1211 emit_movtomro(as, REX_64IR(irkey, src), tmp, 0);
1212 } else if (!irt_ispri(irkey->t)) {
1213 emit_movmroi(as, tmp, 0, irkey->i);
1214 }
1215 if (!(LJ_64 && irt_islightud(irkey->t)))
1216 emit_movmroi(as, tmp, 4, irt_toitype(irkey->t));
1217 emit_loada(as, tmp, &J2G(as->J)->tmptv);
1218 }
1219}
1220
1221static void asm_uref(ASMState *as, IRIns *ir)
1222{
1223 Reg dest = ra_dest(as, ir, RSET_GPR);
1224 if (irref_isk(ir->op1)) {
1225 GCfunc *fn = ir_kfunc(IR(ir->op1));
1226 MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
1227 emit_rma(as, XO_MOV, dest, v);
1228 } else {
1229 Reg uv = ra_scratch(as, RSET_GPR);
1230 Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
1231 if (ir->o == IR_UREFC) {
1232 emit_rmro(as, XO_LEA, dest, uv, offsetof(GCupval, tv));
1233 asm_guardcc(as, CC_NE);
1234 emit_i8(as, 1);
1235 emit_rmro(as, XO_ARITHib, XOg_CMP, uv, offsetof(GCupval, closed));
1236 } else {
1237 emit_rmro(as, XO_MOV, dest, uv, offsetof(GCupval, v));
1238 }
1239 emit_rmro(as, XO_MOV, uv, func,
1240 (int32_t)offsetof(GCfuncL, uvptr) + 4*(int32_t)(ir->op2 >> 8));
1241 }
1242}
1243
1244static void asm_fref(ASMState *as, IRIns *ir)
1245{
1246 Reg dest = ra_dest(as, ir, RSET_GPR);
1247 asm_fusefref(as, ir, RSET_GPR);
1248 emit_mrm(as, XO_LEA, dest, RID_MRM);
1249}
1250
1251static void asm_strref(ASMState *as, IRIns *ir)
1252{
1253 Reg dest = ra_dest(as, ir, RSET_GPR);
1254 asm_fusestrref(as, ir, RSET_GPR);
1255 if (as->mrm.base == RID_NONE)
1256 emit_loadi(as, dest, as->mrm.ofs);
1257 else if (as->mrm.base == dest && as->mrm.idx == RID_NONE)
1258 emit_gri(as, XG_ARITHi(XOg_ADD), dest, as->mrm.ofs);
1259 else
1260 emit_mrm(as, XO_LEA, dest, RID_MRM);
1261}
1262
1263/* -- Loads and stores ---------------------------------------------------- */
1264
1265static void asm_fxload(ASMState *as, IRIns *ir)
1266{
1267 Reg dest = ra_dest(as, ir, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
1268 x86Op xo;
1269 if (ir->o == IR_FLOAD)
1270 asm_fusefref(as, ir, RSET_GPR);
1271 else
1272 asm_fusexref(as, ir->op1, RSET_GPR);
1273 /* ir->op2 is ignored -- unaligned loads are ok on x86. */
1274 switch (irt_type(ir->t)) {
1275 case IRT_I8: xo = XO_MOVSXb; break;
1276 case IRT_U8: xo = XO_MOVZXb; break;
1277 case IRT_I16: xo = XO_MOVSXw; break;
1278 case IRT_U16: xo = XO_MOVZXw; break;
1279 case IRT_NUM: xo = XMM_MOVRM(as); break;
1280 case IRT_FLOAT: xo = XO_MOVSS; break;
1281 default:
1282 if (LJ_64 && irt_is64(ir->t))
1283 dest |= REX_64;
1284 else
1285 lua_assert(irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t));
1286 xo = XO_MOV;
1287 break;
1288 }
1289 emit_mrm(as, xo, dest, RID_MRM);
1290}
1291
1292static void asm_fxstore(ASMState *as, IRIns *ir)
1293{
1294 RegSet allow = RSET_GPR;
1295 Reg src = RID_NONE, osrc = RID_NONE;
1296 int32_t k = 0;
1297 if (ir->r == RID_SINK)
1298 return;
1299 /* The IRT_I16/IRT_U16 stores should never be simplified for constant
1300 ** values since mov word [mem], imm16 has a length-changing prefix.
1301 */
1302 if (irt_isi16(ir->t) || irt_isu16(ir->t) || irt_isfp(ir->t) ||
1303 !asm_isk32(as, ir->op2, &k)) {
1304 RegSet allow8 = irt_isfp(ir->t) ? RSET_FPR :
1305 (irt_isi8(ir->t) || irt_isu8(ir->t)) ? RSET_GPR8 : RSET_GPR;
1306 src = osrc = ra_alloc1(as, ir->op2, allow8);
1307 if (!LJ_64 && !rset_test(allow8, src)) { /* Already in wrong register. */
1308 rset_clear(allow, osrc);
1309 src = ra_scratch(as, allow8);
1310 }
1311 rset_clear(allow, src);
1312 }
1313 if (ir->o == IR_FSTORE) {
1314 asm_fusefref(as, IR(ir->op1), allow);
1315 } else {
1316 asm_fusexref(as, ir->op1, allow);
1317 if (LJ_32 && ir->o == IR_HIOP) as->mrm.ofs += 4;
1318 }
1319 if (ra_hasreg(src)) {
1320 x86Op xo;
1321 switch (irt_type(ir->t)) {
1322 case IRT_I8: case IRT_U8: xo = XO_MOVtob; src |= FORCE_REX; break;
1323 case IRT_I16: case IRT_U16: xo = XO_MOVtow; break;
1324 case IRT_NUM: xo = XO_MOVSDto; break;
1325 case IRT_FLOAT: xo = XO_MOVSSto; break;
1326#if LJ_64
1327 case IRT_LIGHTUD: lua_assert(0); /* NYI: mask 64 bit lightuserdata. */
1328#endif
1329 default:
1330 if (LJ_64 && irt_is64(ir->t))
1331 src |= REX_64;
1332 else
1333 lua_assert(irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t));
1334 xo = XO_MOVto;
1335 break;
1336 }
1337 emit_mrm(as, xo, src, RID_MRM);
1338 if (!LJ_64 && src != osrc) {
1339 ra_noweak(as, osrc);
1340 emit_rr(as, XO_MOV, src, osrc);
1341 }
1342 } else {
1343 if (irt_isi8(ir->t) || irt_isu8(ir->t)) {
1344 emit_i8(as, k);
1345 emit_mrm(as, XO_MOVmib, 0, RID_MRM);
1346 } else {
1347 lua_assert(irt_is64(ir->t) || irt_isint(ir->t) || irt_isu32(ir->t) ||
1348 irt_isaddr(ir->t));
1349 emit_i32(as, k);
1350 emit_mrm(as, XO_MOVmi, REX_64IR(ir, 0), RID_MRM);
1351 }
1352 }
1353}
1354
1355#if LJ_64
1356static Reg asm_load_lightud64(ASMState *as, IRIns *ir, int typecheck)
1357{
1358 if (ra_used(ir) || typecheck) {
1359 Reg dest = ra_dest(as, ir, RSET_GPR);
1360 if (typecheck) {
1361 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, dest));
1362 asm_guardcc(as, CC_NE);
1363 emit_i8(as, -2);
1364 emit_rr(as, XO_ARITHi8, XOg_CMP, tmp);
1365 emit_shifti(as, XOg_SAR|REX_64, tmp, 47);
1366 emit_rr(as, XO_MOV, tmp|REX_64, dest);
1367 }
1368 return dest;
1369 } else {
1370 return RID_NONE;
1371 }
1372}
1373#endif
1374
1375static void asm_ahuvload(ASMState *as, IRIns *ir)
1376{
1377 lua_assert(irt_isnum(ir->t) || irt_ispri(ir->t) || irt_isaddr(ir->t) ||
1378 (LJ_DUALNUM && irt_isint(ir->t)));
1379#if LJ_64
1380 if (irt_islightud(ir->t)) {
1381 Reg dest = asm_load_lightud64(as, ir, 1);
1382 if (ra_hasreg(dest)) {
1383 checkmclim(as);
1384 asm_fuseahuref(as, ir->op1, RSET_GPR);
1385 emit_mrm(as, XO_MOV, dest|REX_64, RID_MRM);
1386 }
1387 return;
1388 } else
1389#endif
1390 if (ra_used(ir)) {
1391 RegSet allow = irt_isnum(ir->t) ? RSET_FPR : RSET_GPR;
1392 Reg dest = ra_dest(as, ir, allow);
1393 asm_fuseahuref(as, ir->op1, RSET_GPR);
1394 emit_mrm(as, dest < RID_MAX_GPR ? XO_MOV : XMM_MOVRM(as), dest, RID_MRM);
1395 } else {
1396 asm_fuseahuref(as, ir->op1, RSET_GPR);
1397 }
1398 /* Always do the type check, even if the load result is unused. */
1399 as->mrm.ofs += 4;
1400 asm_guardcc(as, irt_isnum(ir->t) ? CC_AE : CC_NE);
1401 if (LJ_64 && irt_type(ir->t) >= IRT_NUM) {
1402 lua_assert(irt_isinteger(ir->t) || irt_isnum(ir->t));
1403 checkmclim(as);
1404 emit_u32(as, LJ_TISNUM);
1405 emit_mrm(as, XO_ARITHi, XOg_CMP, RID_MRM);
1406 } else {
1407 emit_i8(as, irt_toitype(ir->t));
1408 emit_mrm(as, XO_ARITHi8, XOg_CMP, RID_MRM);
1409 }
1410}
1411
1412static void asm_ahustore(ASMState *as, IRIns *ir)
1413{
1414 if (ir->r == RID_SINK)
1415 return;
1416 if (irt_isnum(ir->t)) {
1417 Reg src = ra_alloc1(as, ir->op2, RSET_FPR);
1418 asm_fuseahuref(as, ir->op1, RSET_GPR);
1419 emit_mrm(as, XO_MOVSDto, src, RID_MRM);
1420#if LJ_64
1421 } else if (irt_islightud(ir->t)) {
1422 Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
1423 asm_fuseahuref(as, ir->op1, rset_exclude(RSET_GPR, src));
1424 emit_mrm(as, XO_MOVto, src|REX_64, RID_MRM);
1425#endif
1426 } else {
1427 IRIns *irr = IR(ir->op2);
1428 RegSet allow = RSET_GPR;
1429 Reg src = RID_NONE;
1430 if (!irref_isk(ir->op2)) {
1431 src = ra_alloc1(as, ir->op2, allow);
1432 rset_clear(allow, src);
1433 }
1434 asm_fuseahuref(as, ir->op1, allow);
1435 if (ra_hasreg(src)) {
1436 emit_mrm(as, XO_MOVto, src, RID_MRM);
1437 } else if (!irt_ispri(irr->t)) {
1438 lua_assert(irt_isaddr(ir->t) || (LJ_DUALNUM && irt_isinteger(ir->t)));
1439 emit_i32(as, irr->i);
1440 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
1441 }
1442 as->mrm.ofs += 4;
1443 emit_i32(as, (int32_t)irt_toitype(ir->t));
1444 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
1445 }
1446}
1447
1448static void asm_sload(ASMState *as, IRIns *ir)
1449{
1450 int32_t ofs = 8*((int32_t)ir->op1-1) + ((ir->op2 & IRSLOAD_FRAME) ? 4 : 0);
1451 IRType1 t = ir->t;
1452 Reg base;
1453 lua_assert(!(ir->op2 & IRSLOAD_PARENT)); /* Handled by asm_head_side(). */
1454 lua_assert(irt_isguard(t) || !(ir->op2 & IRSLOAD_TYPECHECK));
1455 lua_assert(LJ_DUALNUM ||
1456 !irt_isint(t) || (ir->op2 & (IRSLOAD_CONVERT|IRSLOAD_FRAME)));
1457 if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t) && irt_isint(t)) {
1458 Reg left = ra_scratch(as, RSET_FPR);
1459 asm_tointg(as, ir, left); /* Frees dest reg. Do this before base alloc. */
1460 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1461 emit_rmro(as, XMM_MOVRM(as), left, base, ofs);
1462 t.irt = IRT_NUM; /* Continue with a regular number type check. */
1463#if LJ_64
1464 } else if (irt_islightud(t)) {
1465 Reg dest = asm_load_lightud64(as, ir, (ir->op2 & IRSLOAD_TYPECHECK));
1466 if (ra_hasreg(dest)) {
1467 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1468 emit_rmro(as, XO_MOV, dest|REX_64, base, ofs);
1469 }
1470 return;
1471#endif
1472 } else if (ra_used(ir)) {
1473 RegSet allow = irt_isnum(t) ? RSET_FPR : RSET_GPR;
1474 Reg dest = ra_dest(as, ir, allow);
1475 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1476 lua_assert(irt_isnum(t) || irt_isint(t) || irt_isaddr(t));
1477 if ((ir->op2 & IRSLOAD_CONVERT)) {
1478 t.irt = irt_isint(t) ? IRT_NUM : IRT_INT; /* Check for original type. */
1479 emit_rmro(as, irt_isint(t) ? XO_CVTSI2SD : XO_CVTSD2SI, dest, base, ofs);
1480 } else if (irt_isnum(t)) {
1481 emit_rmro(as, XMM_MOVRM(as), dest, base, ofs);
1482 } else {
1483 emit_rmro(as, XO_MOV, dest, base, ofs);
1484 }
1485 } else {
1486 if (!(ir->op2 & IRSLOAD_TYPECHECK))
1487 return; /* No type check: avoid base alloc. */
1488 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1489 }
1490 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1491 /* Need type check, even if the load result is unused. */
1492 asm_guardcc(as, irt_isnum(t) ? CC_AE : CC_NE);
1493 if (LJ_64 && irt_type(t) >= IRT_NUM) {
1494 lua_assert(irt_isinteger(t) || irt_isnum(t));
1495 emit_u32(as, LJ_TISNUM);
1496 emit_rmro(as, XO_ARITHi, XOg_CMP, base, ofs+4);
1497 } else {
1498 emit_i8(as, irt_toitype(t));
1499 emit_rmro(as, XO_ARITHi8, XOg_CMP, base, ofs+4);
1500 }
1501 }
1502}
1503
1504/* -- Allocations --------------------------------------------------------- */
1505
1506#if LJ_HASFFI
1507static void asm_cnew(ASMState *as, IRIns *ir)
1508{
1509 CTState *cts = ctype_ctsG(J2G(as->J));
1510 CTypeID ctypeid = (CTypeID)IR(ir->op1)->i;
1511 CTSize sz = (ir->o == IR_CNEWI || ir->op2 == REF_NIL) ?
1512 lj_ctype_size(cts, ctypeid) : (CTSize)IR(ir->op2)->i;
1513 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
1514 IRRef args[2];
1515 lua_assert(sz != CTSIZE_INVALID);
1516
1517 args[0] = ASMREF_L; /* lua_State *L */
1518 args[1] = ASMREF_TMP1; /* MSize size */
1519 as->gcsteps++;
1520 asm_setupresult(as, ir, ci); /* GCcdata * */
1521
1522 /* Initialize immutable cdata object. */
1523 if (ir->o == IR_CNEWI) {
1524 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
1525#if LJ_64
1526 Reg r64 = sz == 8 ? REX_64 : 0;
1527 if (irref_isk(ir->op2)) {
1528 IRIns *irk = IR(ir->op2);
1529 uint64_t k = irk->o == IR_KINT64 ? ir_k64(irk)->u64 :
1530 (uint64_t)(uint32_t)irk->i;
1531 if (sz == 4 || checki32((int64_t)k)) {
1532 emit_i32(as, (int32_t)k);
1533 emit_rmro(as, XO_MOVmi, r64, RID_RET, sizeof(GCcdata));
1534 } else {
1535 emit_movtomro(as, RID_ECX + r64, RID_RET, sizeof(GCcdata));
1536 emit_loadu64(as, RID_ECX, k);
1537 }
1538 } else {
1539 Reg r = ra_alloc1(as, ir->op2, allow);
1540 emit_movtomro(as, r + r64, RID_RET, sizeof(GCcdata));
1541 }
1542#else
1543 int32_t ofs = sizeof(GCcdata);
1544 if (sz == 8) {
1545 ofs += 4; ir++;
1546 lua_assert(ir->o == IR_HIOP);
1547 }
1548 do {
1549 if (irref_isk(ir->op2)) {
1550 emit_movmroi(as, RID_RET, ofs, IR(ir->op2)->i);
1551 } else {
1552 Reg r = ra_alloc1(as, ir->op2, allow);
1553 emit_movtomro(as, r, RID_RET, ofs);
1554 rset_clear(allow, r);
1555 }
1556 if (ofs == sizeof(GCcdata)) break;
1557 ofs -= 4; ir--;
1558 } while (1);
1559#endif
1560 lua_assert(sz == 4 || sz == 8);
1561 }
1562
1563 /* Combine initialization of marked, gct and ctypeid. */
1564 emit_movtomro(as, RID_ECX, RID_RET, offsetof(GCcdata, marked));
1565 emit_gri(as, XG_ARITHi(XOg_OR), RID_ECX,
1566 (int32_t)((~LJ_TCDATA<<8)+(ctypeid<<16)));
1567 emit_gri(as, XG_ARITHi(XOg_AND), RID_ECX, LJ_GC_WHITES);
1568 emit_opgl(as, XO_MOVZXb, RID_ECX, gc.currentwhite);
1569
1570 asm_gencall(as, ci, args);
1571 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)(sz+sizeof(GCcdata)));
1572}
1573#else
1574#define asm_cnew(as, ir) ((void)0)
1575#endif
1576
1577/* -- Write barriers ------------------------------------------------------ */
1578
1579static void asm_tbar(ASMState *as, IRIns *ir)
1580{
1581 Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
1582 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, tab));
1583 MCLabel l_end = emit_label(as);
1584 emit_movtomro(as, tmp, tab, offsetof(GCtab, gclist));
1585 emit_setgl(as, tab, gc.grayagain);
1586 emit_getgl(as, tmp, gc.grayagain);
1587 emit_i8(as, ~LJ_GC_BLACK);
1588 emit_rmro(as, XO_ARITHib, XOg_AND, tab, offsetof(GCtab, marked));
1589 emit_sjcc(as, CC_Z, l_end);
1590 emit_i8(as, LJ_GC_BLACK);
1591 emit_rmro(as, XO_GROUP3b, XOg_TEST, tab, offsetof(GCtab, marked));
1592}
1593
1594static void asm_obar(ASMState *as, IRIns *ir)
1595{
1596 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
1597 IRRef args[2];
1598 MCLabel l_end;
1599 Reg obj;
1600 /* No need for other object barriers (yet). */
1601 lua_assert(IR(ir->op1)->o == IR_UREFC);
1602 ra_evictset(as, RSET_SCRATCH);
1603 l_end = emit_label(as);
1604 args[0] = ASMREF_TMP1; /* global_State *g */
1605 args[1] = ir->op1; /* TValue *tv */
1606 asm_gencall(as, ci, args);
1607 emit_loada(as, ra_releasetmp(as, ASMREF_TMP1), J2G(as->J));
1608 obj = IR(ir->op1)->r;
1609 emit_sjcc(as, CC_Z, l_end);
1610 emit_i8(as, LJ_GC_WHITES);
1611 if (irref_isk(ir->op2)) {
1612 GCobj *vp = ir_kgc(IR(ir->op2));
1613 emit_rma(as, XO_GROUP3b, XOg_TEST, &vp->gch.marked);
1614 } else {
1615 Reg val = ra_alloc1(as, ir->op2, rset_exclude(RSET_SCRATCH&RSET_GPR, obj));
1616 emit_rmro(as, XO_GROUP3b, XOg_TEST, val, (int32_t)offsetof(GChead, marked));
1617 }
1618 emit_sjcc(as, CC_Z, l_end);
1619 emit_i8(as, LJ_GC_BLACK);
1620 emit_rmro(as, XO_GROUP3b, XOg_TEST, obj,
1621 (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
1622}
1623
1624/* -- FP/int arithmetic and logic operations ------------------------------ */
1625
1626/* Load reference onto x87 stack. Force a spill to memory if needed. */
1627static void asm_x87load(ASMState *as, IRRef ref)
1628{
1629 IRIns *ir = IR(ref);
1630 if (ir->o == IR_KNUM) {
1631 cTValue *tv = ir_knum(ir);
1632 if (tvispzero(tv)) /* Use fldz only for +0. */
1633 emit_x87op(as, XI_FLDZ);
1634 else if (tvispone(tv))
1635 emit_x87op(as, XI_FLD1);
1636 else
1637 emit_rma(as, XO_FLDq, XOg_FLDq, tv);
1638 } else if (ir->o == IR_CONV && ir->op2 == IRCONV_NUM_INT && !ra_used(ir) &&
1639 !irref_isk(ir->op1) && mayfuse(as, ir->op1)) {
1640 IRIns *iri = IR(ir->op1);
1641 emit_rmro(as, XO_FILDd, XOg_FILDd, RID_ESP, ra_spill(as, iri));
1642 } else {
1643 emit_mrm(as, XO_FLDq, XOg_FLDq, asm_fuseload(as, ref, RSET_EMPTY));
1644 }
1645}
1646
1647/* Try to rejoin pow from EXP2, MUL and LOG2 (if still unsplit). */
1648static int fpmjoin_pow(ASMState *as, IRIns *ir)
1649{
1650 IRIns *irp = IR(ir->op1);
1651 if (irp == ir-1 && irp->o == IR_MUL && !ra_used(irp)) {
1652 IRIns *irpp = IR(irp->op1);
1653 if (irpp == ir-2 && irpp->o == IR_FPMATH &&
1654 irpp->op2 == IRFPM_LOG2 && !ra_used(irpp)) {
1655 /* The modified regs must match with the *.dasc implementation. */
1656 RegSet drop = RSET_RANGE(RID_XMM0, RID_XMM2+1)|RID2RSET(RID_EAX);
1657 IRIns *irx;
1658 if (ra_hasreg(ir->r))
1659 rset_clear(drop, ir->r); /* Dest reg handled below. */
1660 ra_evictset(as, drop);
1661 ra_destreg(as, ir, RID_XMM0);
1662 emit_call(as, lj_vm_pow_sse);
1663 irx = IR(irpp->op1);
1664 if (ra_noreg(irx->r) && ra_gethint(irx->r) == RID_XMM1)
1665 irx->r = RID_INIT; /* Avoid allocating xmm1 for x. */
1666 ra_left(as, RID_XMM0, irpp->op1);
1667 ra_left(as, RID_XMM1, irp->op2);
1668 return 1;
1669 }
1670 }
1671 return 0;
1672}
1673
1674static void asm_fpmath(ASMState *as, IRIns *ir)
1675{
1676 IRFPMathOp fpm = ir->o == IR_FPMATH ? (IRFPMathOp)ir->op2 : IRFPM_OTHER;
1677 if (fpm == IRFPM_SQRT) {
1678 Reg dest = ra_dest(as, ir, RSET_FPR);
1679 Reg left = asm_fuseload(as, ir->op1, RSET_FPR);
1680 emit_mrm(as, XO_SQRTSD, dest, left);
1681 } else if (fpm <= IRFPM_TRUNC) {
1682 if (as->flags & JIT_F_SSE4_1) { /* SSE4.1 has a rounding instruction. */
1683 Reg dest = ra_dest(as, ir, RSET_FPR);
1684 Reg left = asm_fuseload(as, ir->op1, RSET_FPR);
1685 /* ROUNDSD has a 4-byte opcode which doesn't fit in x86Op.
1686 ** Let's pretend it's a 3-byte opcode, and compensate afterwards.
1687 ** This is atrocious, but the alternatives are much worse.
1688 */
1689 /* Round down/up/trunc == 1001/1010/1011. */
1690 emit_i8(as, 0x09 + fpm);
1691 emit_mrm(as, XO_ROUNDSD, dest, left);
1692 if (LJ_64 && as->mcp[1] != (MCode)(XO_ROUNDSD >> 16)) {
1693 as->mcp[0] = as->mcp[1]; as->mcp[1] = 0x0f; /* Swap 0F and REX. */
1694 }
1695 *--as->mcp = 0x66; /* 1st byte of ROUNDSD opcode. */
1696 } else { /* Call helper functions for SSE2 variant. */
1697 /* The modified regs must match with the *.dasc implementation. */
1698 RegSet drop = RSET_RANGE(RID_XMM0, RID_XMM3+1)|RID2RSET(RID_EAX);
1699 if (ra_hasreg(ir->r))
1700 rset_clear(drop, ir->r); /* Dest reg handled below. */
1701 ra_evictset(as, drop);
1702 ra_destreg(as, ir, RID_XMM0);
1703 emit_call(as, fpm == IRFPM_FLOOR ? lj_vm_floor_sse :
1704 fpm == IRFPM_CEIL ? lj_vm_ceil_sse : lj_vm_trunc_sse);
1705 ra_left(as, RID_XMM0, ir->op1);
1706 }
1707 } else if (fpm == IRFPM_EXP2 && fpmjoin_pow(as, ir)) {
1708 /* Rejoined to pow(). */
1709 } else { /* Handle x87 ops. */
1710 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
1711 Reg dest = ir->r;
1712 if (ra_hasreg(dest)) {
1713 ra_free(as, dest);
1714 ra_modified(as, dest);
1715 emit_rmro(as, XMM_MOVRM(as), dest, RID_ESP, ofs);
1716 }
1717 emit_rmro(as, XO_FSTPq, XOg_FSTPq, RID_ESP, ofs);
1718 switch (fpm) { /* st0 = lj_vm_*(st0) */
1719 case IRFPM_EXP: emit_call(as, lj_vm_exp_x87); break;
1720 case IRFPM_EXP2: emit_call(as, lj_vm_exp2_x87); break;
1721 case IRFPM_SIN: emit_x87op(as, XI_FSIN); break;
1722 case IRFPM_COS: emit_x87op(as, XI_FCOS); break;
1723 case IRFPM_TAN: emit_x87op(as, XI_FPOP); emit_x87op(as, XI_FPTAN); break;
1724 case IRFPM_LOG: case IRFPM_LOG2: case IRFPM_LOG10:
1725 /* Note: the use of fyl2xp1 would be pointless here. When computing
1726 ** log(1.0+eps) the precision is already lost after 1.0 is added.
1727 ** Subtracting 1.0 won't recover it. OTOH math.log1p would make sense.
1728 */
1729 emit_x87op(as, XI_FYL2X); break;
1730 case IRFPM_OTHER:
1731 switch (ir->o) {
1732 case IR_ATAN2:
1733 emit_x87op(as, XI_FPATAN); asm_x87load(as, ir->op2); break;
1734 case IR_LDEXP:
1735 emit_x87op(as, XI_FPOP1); emit_x87op(as, XI_FSCALE); break;
1736 default: lua_assert(0); break;
1737 }
1738 break;
1739 default: lua_assert(0); break;
1740 }
1741 asm_x87load(as, ir->op1);
1742 switch (fpm) {
1743 case IRFPM_LOG: emit_x87op(as, XI_FLDLN2); break;
1744 case IRFPM_LOG2: emit_x87op(as, XI_FLD1); break;
1745 case IRFPM_LOG10: emit_x87op(as, XI_FLDLG2); break;
1746 case IRFPM_OTHER:
1747 if (ir->o == IR_LDEXP) asm_x87load(as, ir->op2);
1748 break;
1749 default: break;
1750 }
1751 }
1752}
1753
1754static void asm_fppowi(ASMState *as, IRIns *ir)
1755{
1756 /* The modified regs must match with the *.dasc implementation. */
1757 RegSet drop = RSET_RANGE(RID_XMM0, RID_XMM1+1)|RID2RSET(RID_EAX);
1758 if (ra_hasreg(ir->r))
1759 rset_clear(drop, ir->r); /* Dest reg handled below. */
1760 ra_evictset(as, drop);
1761 ra_destreg(as, ir, RID_XMM0);
1762 emit_call(as, lj_vm_powi_sse);
1763 ra_left(as, RID_XMM0, ir->op1);
1764 ra_left(as, RID_EAX, ir->op2);
1765}
1766
1767#if LJ_64 && LJ_HASFFI
1768static void asm_arith64(ASMState *as, IRIns *ir, IRCallID id)
1769{
1770 const CCallInfo *ci = &lj_ir_callinfo[id];
1771 IRRef args[2];
1772 args[0] = ir->op1;
1773 args[1] = ir->op2;
1774 asm_setupresult(as, ir, ci);
1775 asm_gencall(as, ci, args);
1776}
1777#endif
1778
1779static void asm_intmod(ASMState *as, IRIns *ir)
1780{
1781 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_vm_modi];
1782 IRRef args[2];
1783 args[0] = ir->op1;
1784 args[1] = ir->op2;
1785 asm_setupresult(as, ir, ci);
1786 asm_gencall(as, ci, args);
1787}
1788
1789static int asm_swapops(ASMState *as, IRIns *ir)
1790{
1791 IRIns *irl = IR(ir->op1);
1792 IRIns *irr = IR(ir->op2);
1793 lua_assert(ra_noreg(irr->r));
1794 if (!irm_iscomm(lj_ir_mode[ir->o]))
1795 return 0; /* Can't swap non-commutative operations. */
1796 if (irref_isk(ir->op2))
1797 return 0; /* Don't swap constants to the left. */
1798 if (ra_hasreg(irl->r))
1799 return 1; /* Swap if left already has a register. */
1800 if (ra_samehint(ir->r, irr->r))
1801 return 1; /* Swap if dest and right have matching hints. */
1802 if (as->curins > as->loopref) { /* In variant part? */
1803 if (ir->op2 < as->loopref && !irt_isphi(irr->t))
1804 return 0; /* Keep invariants on the right. */
1805 if (ir->op1 < as->loopref && !irt_isphi(irl->t))
1806 return 1; /* Swap invariants to the right. */
1807 }
1808 if (opisfusableload(irl->o))
1809 return 1; /* Swap fusable loads to the right. */
1810 return 0; /* Otherwise don't swap. */
1811}
1812
1813static void asm_fparith(ASMState *as, IRIns *ir, x86Op xo)
1814{
1815 IRRef lref = ir->op1;
1816 IRRef rref = ir->op2;
1817 RegSet allow = RSET_FPR;
1818 Reg dest;
1819 Reg right = IR(rref)->r;
1820 if (ra_hasreg(right)) {
1821 rset_clear(allow, right);
1822 ra_noweak(as, right);
1823 }
1824 dest = ra_dest(as, ir, allow);
1825 if (lref == rref) {
1826 right = dest;
1827 } else if (ra_noreg(right)) {
1828 if (asm_swapops(as, ir)) {
1829 IRRef tmp = lref; lref = rref; rref = tmp;
1830 }
1831 right = asm_fuseload(as, rref, rset_clear(allow, dest));
1832 }
1833 emit_mrm(as, xo, dest, right);
1834 ra_left(as, dest, lref);
1835}
1836
1837static void asm_intarith(ASMState *as, IRIns *ir, x86Arith xa)
1838{
1839 IRRef lref = ir->op1;
1840 IRRef rref = ir->op2;
1841 RegSet allow = RSET_GPR;
1842 Reg dest, right;
1843 int32_t k = 0;
1844 if (as->flagmcp == as->mcp && xa != XOg_X_IMUL) {
1845 /* Drop test r,r instruction. */
1846 MCode *p = as->mcp + ((LJ_64 && *as->mcp < XI_TESTb) ? 3 : 2);
1847 MCode *q = p[0] == 0x0f ? p+1 : p;
1848 if ((*q & 15) < 14) {
1849 if ((*q & 15) >= 12) *q -= 4; /* L <->S, NL <-> NS */
1850 as->flagmcp = NULL;
1851 as->mcp = p;
1852 } /* else: cannot transform LE/NLE to cc without use of OF. */
1853 }
1854 right = IR(rref)->r;
1855 if (ra_hasreg(right)) {
1856 rset_clear(allow, right);
1857 ra_noweak(as, right);
1858 }
1859 dest = ra_dest(as, ir, allow);
1860 if (lref == rref) {
1861 right = dest;
1862 } else if (ra_noreg(right) && !asm_isk32(as, rref, &k)) {
1863 if (asm_swapops(as, ir)) {
1864 IRRef tmp = lref; lref = rref; rref = tmp;
1865 }
1866 right = asm_fuseloadm(as, rref, rset_clear(allow, dest), irt_is64(ir->t));
1867 }
1868 if (irt_isguard(ir->t)) /* For IR_ADDOV etc. */
1869 asm_guardcc(as, CC_O);
1870 if (xa != XOg_X_IMUL) {
1871 if (ra_hasreg(right))
1872 emit_mrm(as, XO_ARITH(xa), REX_64IR(ir, dest), right);
1873 else
1874 emit_gri(as, XG_ARITHi(xa), REX_64IR(ir, dest), k);
1875 } else if (ra_hasreg(right)) { /* IMUL r, mrm. */
1876 emit_mrm(as, XO_IMUL, REX_64IR(ir, dest), right);
1877 } else { /* IMUL r, r, k. */
1878 /* NYI: use lea/shl/add/sub (FOLD only does 2^k) depending on CPU. */
1879 Reg left = asm_fuseloadm(as, lref, RSET_GPR, irt_is64(ir->t));
1880 x86Op xo;
1881 if (checki8(k)) { emit_i8(as, k); xo = XO_IMULi8;
1882 } else { emit_i32(as, k); xo = XO_IMULi; }
1883 emit_mrm(as, xo, REX_64IR(ir, dest), left);
1884 return;
1885 }
1886 ra_left(as, dest, lref);
1887}
1888
1889/* LEA is really a 4-operand ADD with an independent destination register,
1890** up to two source registers and an immediate. One register can be scaled
1891** by 1, 2, 4 or 8. This can be used to avoid moves or to fuse several
1892** instructions.
1893**
1894** Currently only a few common cases are supported:
1895** - 3-operand ADD: y = a+b; y = a+k with a and b already allocated
1896** - Left ADD fusion: y = (a+b)+k; y = (a+k)+b
1897** - Right ADD fusion: y = a+(b+k)
1898** The ommited variants have already been reduced by FOLD.
1899**
1900** There are more fusion opportunities, like gathering shifts or joining
1901** common references. But these are probably not worth the trouble, since
1902** array indexing is not decomposed and already makes use of all fields
1903** of the ModRM operand.
1904*/
1905static int asm_lea(ASMState *as, IRIns *ir)
1906{
1907 IRIns *irl = IR(ir->op1);
1908 IRIns *irr = IR(ir->op2);
1909 RegSet allow = RSET_GPR;
1910 Reg dest;
1911 as->mrm.base = as->mrm.idx = RID_NONE;
1912 as->mrm.scale = XM_SCALE1;
1913 as->mrm.ofs = 0;
1914 if (ra_hasreg(irl->r)) {
1915 rset_clear(allow, irl->r);
1916 ra_noweak(as, irl->r);
1917 as->mrm.base = irl->r;
1918 if (irref_isk(ir->op2) || ra_hasreg(irr->r)) {
1919 /* The PHI renaming logic does a better job in some cases. */
1920 if (ra_hasreg(ir->r) &&
1921 ((irt_isphi(irl->t) && as->phireg[ir->r] == ir->op1) ||
1922 (irt_isphi(irr->t) && as->phireg[ir->r] == ir->op2)))
1923 return 0;
1924 if (irref_isk(ir->op2)) {
1925 as->mrm.ofs = irr->i;
1926 } else {
1927 rset_clear(allow, irr->r);
1928 ra_noweak(as, irr->r);
1929 as->mrm.idx = irr->r;
1930 }
1931 } else if (irr->o == IR_ADD && mayfuse(as, ir->op2) &&
1932 irref_isk(irr->op2)) {
1933 Reg idx = ra_alloc1(as, irr->op1, allow);
1934 rset_clear(allow, idx);
1935 as->mrm.idx = (uint8_t)idx;
1936 as->mrm.ofs = IR(irr->op2)->i;
1937 } else {
1938 return 0;
1939 }
1940 } else if (ir->op1 != ir->op2 && irl->o == IR_ADD && mayfuse(as, ir->op1) &&
1941 (irref_isk(ir->op2) || irref_isk(irl->op2))) {
1942 Reg idx, base = ra_alloc1(as, irl->op1, allow);
1943 rset_clear(allow, base);
1944 as->mrm.base = (uint8_t)base;
1945 if (irref_isk(ir->op2)) {
1946 as->mrm.ofs = irr->i;
1947 idx = ra_alloc1(as, irl->op2, allow);
1948 } else {
1949 as->mrm.ofs = IR(irl->op2)->i;
1950 idx = ra_alloc1(as, ir->op2, allow);
1951 }
1952 rset_clear(allow, idx);
1953 as->mrm.idx = (uint8_t)idx;
1954 } else {
1955 return 0;
1956 }
1957 dest = ra_dest(as, ir, allow);
1958 emit_mrm(as, XO_LEA, dest, RID_MRM);
1959 return 1; /* Success. */
1960}
1961
1962static void asm_add(ASMState *as, IRIns *ir)
1963{
1964 if (irt_isnum(ir->t))
1965 asm_fparith(as, ir, XO_ADDSD);
1966 else if ((as->flags & JIT_F_LEA_AGU) || as->flagmcp == as->mcp ||
1967 irt_is64(ir->t) || !asm_lea(as, ir))
1968 asm_intarith(as, ir, XOg_ADD);
1969}
1970
1971static void asm_neg_not(ASMState *as, IRIns *ir, x86Group3 xg)
1972{
1973 Reg dest = ra_dest(as, ir, RSET_GPR);
1974 emit_rr(as, XO_GROUP3, REX_64IR(ir, xg), dest);
1975 ra_left(as, dest, ir->op1);
1976}
1977
1978static void asm_min_max(ASMState *as, IRIns *ir, int cc)
1979{
1980 Reg right, dest = ra_dest(as, ir, RSET_GPR);
1981 IRRef lref = ir->op1, rref = ir->op2;
1982 if (irref_isk(rref)) { lref = rref; rref = ir->op1; }
1983 right = ra_alloc1(as, rref, rset_exclude(RSET_GPR, dest));
1984 emit_rr(as, XO_CMOV + (cc<<24), REX_64IR(ir, dest), right);
1985 emit_rr(as, XO_CMP, REX_64IR(ir, dest), right);
1986 ra_left(as, dest, lref);
1987}
1988
1989static void asm_bitswap(ASMState *as, IRIns *ir)
1990{
1991 Reg dest = ra_dest(as, ir, RSET_GPR);
1992 as->mcp = emit_op(XO_BSWAP + ((dest&7) << 24),
1993 REX_64IR(ir, 0), dest, 0, as->mcp, 1);
1994 ra_left(as, dest, ir->op1);
1995}
1996
1997static void asm_bitshift(ASMState *as, IRIns *ir, x86Shift xs)
1998{
1999 IRRef rref = ir->op2;
2000 IRIns *irr = IR(rref);
2001 Reg dest;
2002 if (irref_isk(rref)) { /* Constant shifts. */
2003 int shift;
2004 dest = ra_dest(as, ir, RSET_GPR);
2005 shift = irr->i & (irt_is64(ir->t) ? 63 : 31);
2006 switch (shift) {
2007 case 0: break;
2008 case 1: emit_rr(as, XO_SHIFT1, REX_64IR(ir, xs), dest); break;
2009 default: emit_shifti(as, REX_64IR(ir, xs), dest, shift); break;
2010 }
2011 } else { /* Variable shifts implicitly use register cl (i.e. ecx). */
2012 Reg right;
2013 dest = ra_dest(as, ir, rset_exclude(RSET_GPR, RID_ECX));
2014 if (dest == RID_ECX) {
2015 dest = ra_scratch(as, rset_exclude(RSET_GPR, RID_ECX));
2016 emit_rr(as, XO_MOV, RID_ECX, dest);
2017 }
2018 right = irr->r;
2019 if (ra_noreg(right))
2020 right = ra_allocref(as, rref, RID2RSET(RID_ECX));
2021 else if (right != RID_ECX)
2022 ra_scratch(as, RID2RSET(RID_ECX));
2023 emit_rr(as, XO_SHIFTcl, REX_64IR(ir, xs), dest);
2024 ra_noweak(as, right);
2025 if (right != RID_ECX)
2026 emit_rr(as, XO_MOV, RID_ECX, right);
2027 }
2028 ra_left(as, dest, ir->op1);
2029 /*
2030 ** Note: avoid using the flags resulting from a shift or rotate!
2031 ** All of them cause a partial flag stall, except for r,1 shifts
2032 ** (but not rotates). And a shift count of 0 leaves the flags unmodified.
2033 */
2034}
2035
2036/* -- Comparisons --------------------------------------------------------- */
2037
2038/* Virtual flags for unordered FP comparisons. */
2039#define VCC_U 0x1000 /* Unordered. */
2040#define VCC_P 0x2000 /* Needs extra CC_P branch. */
2041#define VCC_S 0x4000 /* Swap avoids CC_P branch. */
2042#define VCC_PS (VCC_P|VCC_S)
2043
2044/* Map of comparisons to flags. ORDER IR. */
2045#define COMPFLAGS(ci, cin, cu, cf) ((ci)+((cu)<<4)+((cin)<<8)+(cf))
2046static const uint16_t asm_compmap[IR_ABC+1] = {
2047 /* signed non-eq unsigned flags */
2048 /* LT */ COMPFLAGS(CC_GE, CC_G, CC_AE, VCC_PS),
2049 /* GE */ COMPFLAGS(CC_L, CC_L, CC_B, 0),
2050 /* LE */ COMPFLAGS(CC_G, CC_G, CC_A, VCC_PS),
2051 /* GT */ COMPFLAGS(CC_LE, CC_L, CC_BE, 0),
2052 /* ULT */ COMPFLAGS(CC_AE, CC_A, CC_AE, VCC_U),
2053 /* UGE */ COMPFLAGS(CC_B, CC_B, CC_B, VCC_U|VCC_PS),
2054 /* ULE */ COMPFLAGS(CC_A, CC_A, CC_A, VCC_U),
2055 /* UGT */ COMPFLAGS(CC_BE, CC_B, CC_BE, VCC_U|VCC_PS),
2056 /* EQ */ COMPFLAGS(CC_NE, CC_NE, CC_NE, VCC_P),
2057 /* NE */ COMPFLAGS(CC_E, CC_E, CC_E, VCC_U|VCC_P),
2058 /* ABC */ COMPFLAGS(CC_BE, CC_B, CC_BE, VCC_U|VCC_PS) /* Same as UGT. */
2059};
2060
2061/* FP and integer comparisons. */
2062static void asm_comp(ASMState *as, IRIns *ir, uint32_t cc)
2063{
2064 if (irt_isnum(ir->t)) {
2065 IRRef lref = ir->op1;
2066 IRRef rref = ir->op2;
2067 Reg left, right;
2068 MCLabel l_around;
2069 /*
2070 ** An extra CC_P branch is required to preserve ordered/unordered
2071 ** semantics for FP comparisons. This can be avoided by swapping
2072 ** the operands and inverting the condition (except for EQ and UNE).
2073 ** So always try to swap if possible.
2074 **
2075 ** Another option would be to swap operands to achieve better memory
2076 ** operand fusion. But it's unlikely that this outweighs the cost
2077 ** of the extra branches.
2078 */
2079 if (cc & VCC_S) { /* Swap? */
2080 IRRef tmp = lref; lref = rref; rref = tmp;
2081 cc ^= (VCC_PS|(5<<4)); /* A <-> B, AE <-> BE, PS <-> none */
2082 }
2083 left = ra_alloc1(as, lref, RSET_FPR);
2084 right = asm_fuseload(as, rref, rset_exclude(RSET_FPR, left));
2085 l_around = emit_label(as);
2086 asm_guardcc(as, cc >> 4);
2087 if (cc & VCC_P) { /* Extra CC_P branch required? */
2088 if (!(cc & VCC_U)) {
2089 asm_guardcc(as, CC_P); /* Branch to exit for ordered comparisons. */
2090 } else if (l_around != as->invmcp) {
2091 emit_sjcc(as, CC_P, l_around); /* Branch around for unordered. */
2092 } else {
2093 /* Patched to mcloop by asm_loop_fixup. */
2094 as->loopinv = 2;
2095 if (as->realign)
2096 emit_sjcc(as, CC_P, as->mcp);
2097 else
2098 emit_jcc(as, CC_P, as->mcp);
2099 }
2100 }
2101 emit_mrm(as, XO_UCOMISD, left, right);
2102 } else {
2103 IRRef lref = ir->op1, rref = ir->op2;
2104 IROp leftop = (IROp)(IR(lref)->o);
2105 Reg r64 = REX_64IR(ir, 0);
2106 int32_t imm = 0;
2107 lua_assert(irt_is64(ir->t) || irt_isint(ir->t) ||
2108 irt_isu32(ir->t) || irt_isaddr(ir->t) || irt_isu8(ir->t));
2109 /* Swap constants (only for ABC) and fusable loads to the right. */
2110 if (irref_isk(lref) || (!irref_isk(rref) && opisfusableload(leftop))) {
2111 if ((cc & 0xc) == 0xc) cc ^= 0x53; /* L <-> G, LE <-> GE */
2112 else if ((cc & 0xa) == 0x2) cc ^= 0x55; /* A <-> B, AE <-> BE */
2113 lref = ir->op2; rref = ir->op1;
2114 }
2115 if (asm_isk32(as, rref, &imm)) {
2116 IRIns *irl = IR(lref);
2117 /* Check wether we can use test ins. Not for unsigned, since CF=0. */
2118 int usetest = (imm == 0 && (cc & 0xa) != 0x2);
2119 if (usetest && irl->o == IR_BAND && irl+1 == ir && !ra_used(irl)) {
2120 /* Combine comp(BAND(ref, r/imm), 0) into test mrm, r/imm. */
2121 Reg right, left = RID_NONE;
2122 RegSet allow = RSET_GPR;
2123 if (!asm_isk32(as, irl->op2, &imm)) {
2124 left = ra_alloc1(as, irl->op2, allow);
2125 rset_clear(allow, left);
2126 } else { /* Try to Fuse IRT_I8/IRT_U8 loads, too. See below. */
2127 IRIns *irll = IR(irl->op1);
2128 if (opisfusableload((IROp)irll->o) &&
2129 (irt_isi8(irll->t) || irt_isu8(irll->t))) {
2130 IRType1 origt = irll->t; /* Temporarily flip types. */
2131 irll->t.irt = (irll->t.irt & ~IRT_TYPE) | IRT_INT;
2132 as->curins--; /* Skip to BAND to avoid failing in noconflict(). */
2133 right = asm_fuseload(as, irl->op1, RSET_GPR);
2134 as->curins++;
2135 irll->t = origt;
2136 if (right != RID_MRM) goto test_nofuse;
2137 /* Fusion succeeded, emit test byte mrm, imm8. */
2138 asm_guardcc(as, cc);
2139 emit_i8(as, (imm & 0xff));
2140 emit_mrm(as, XO_GROUP3b, XOg_TEST, RID_MRM);
2141 return;
2142 }
2143 }
2144 as->curins--; /* Skip to BAND to avoid failing in noconflict(). */
2145 right = asm_fuseloadm(as, irl->op1, allow, r64);
2146 as->curins++; /* Undo the above. */
2147 test_nofuse:
2148 asm_guardcc(as, cc);
2149 if (ra_noreg(left)) {
2150 emit_i32(as, imm);
2151 emit_mrm(as, XO_GROUP3, r64 + XOg_TEST, right);
2152 } else {
2153 emit_mrm(as, XO_TEST, r64 + left, right);
2154 }
2155 } else {
2156 Reg left;
2157 if (opisfusableload((IROp)irl->o) &&
2158 ((irt_isu8(irl->t) && checku8(imm)) ||
2159 ((irt_isi8(irl->t) || irt_isi16(irl->t)) && checki8(imm)) ||
2160 (irt_isu16(irl->t) && checku16(imm) && checki8((int16_t)imm)))) {
2161 /* Only the IRT_INT case is fused by asm_fuseload.
2162 ** The IRT_I8/IRT_U8 loads and some IRT_I16/IRT_U16 loads
2163 ** are handled here.
2164 ** Note that cmp word [mem], imm16 should not be generated,
2165 ** since it has a length-changing prefix. Compares of a word
2166 ** against a sign-extended imm8 are ok, however.
2167 */
2168 IRType1 origt = irl->t; /* Temporarily flip types. */
2169 irl->t.irt = (irl->t.irt & ~IRT_TYPE) | IRT_INT;
2170 left = asm_fuseload(as, lref, RSET_GPR);
2171 irl->t = origt;
2172 if (left == RID_MRM) { /* Fusion succeeded? */
2173 if (irt_isu8(irl->t) || irt_isu16(irl->t))
2174 cc >>= 4; /* Need unsigned compare. */
2175 asm_guardcc(as, cc);
2176 emit_i8(as, imm);
2177 emit_mrm(as, (irt_isi8(origt) || irt_isu8(origt)) ?
2178 XO_ARITHib : XO_ARITHiw8, r64 + XOg_CMP, RID_MRM);
2179 return;
2180 } /* Otherwise handle register case as usual. */
2181 } else {
2182 left = asm_fuseloadm(as, lref,
2183 irt_isu8(ir->t) ? RSET_GPR8 : RSET_GPR, r64);
2184 }
2185 asm_guardcc(as, cc);
2186 if (usetest && left != RID_MRM) {
2187 /* Use test r,r instead of cmp r,0. */
2188 x86Op xo = XO_TEST;
2189 if (irt_isu8(ir->t)) {
2190 lua_assert(ir->o == IR_EQ || ir->o == IR_NE);
2191 xo = XO_TESTb;
2192 if (!rset_test(RSET_RANGE(RID_EAX, RID_EBX+1), left)) {
2193 if (LJ_64) {
2194 left |= FORCE_REX;
2195 } else {
2196 emit_i32(as, 0xff);
2197 emit_mrm(as, XO_GROUP3, XOg_TEST, left);
2198 return;
2199 }
2200 }
2201 }
2202 emit_rr(as, xo, r64 + left, left);
2203 if (irl+1 == ir) /* Referencing previous ins? */
2204 as->flagmcp = as->mcp; /* Set flag to drop test r,r if possible. */
2205 } else {
2206 emit_gmrmi(as, XG_ARITHi(XOg_CMP), r64 + left, imm);
2207 }
2208 }
2209 } else {
2210 Reg left = ra_alloc1(as, lref, RSET_GPR);
2211 Reg right = asm_fuseloadm(as, rref, rset_exclude(RSET_GPR, left), r64);
2212 asm_guardcc(as, cc);
2213 emit_mrm(as, XO_CMP, r64 + left, right);
2214 }
2215 }
2216}
2217
2218#if LJ_32 && LJ_HASFFI
2219/* 64 bit integer comparisons in 32 bit mode. */
2220static void asm_comp_int64(ASMState *as, IRIns *ir)
2221{
2222 uint32_t cc = asm_compmap[(ir-1)->o];
2223 RegSet allow = RSET_GPR;
2224 Reg lefthi = RID_NONE, leftlo = RID_NONE;
2225 Reg righthi = RID_NONE, rightlo = RID_NONE;
2226 MCLabel l_around;
2227 x86ModRM mrm;
2228
2229 as->curins--; /* Skip loword ins. Avoids failing in noconflict(), too. */
2230
2231 /* Allocate/fuse hiword operands. */
2232 if (irref_isk(ir->op2)) {
2233 lefthi = asm_fuseload(as, ir->op1, allow);
2234 } else {
2235 lefthi = ra_alloc1(as, ir->op1, allow);
2236 rset_clear(allow, lefthi);
2237 righthi = asm_fuseload(as, ir->op2, allow);
2238 if (righthi == RID_MRM) {
2239 if (as->mrm.base != RID_NONE) rset_clear(allow, as->mrm.base);
2240 if (as->mrm.idx != RID_NONE) rset_clear(allow, as->mrm.idx);
2241 } else {
2242 rset_clear(allow, righthi);
2243 }
2244 }
2245 mrm = as->mrm; /* Save state for hiword instruction. */
2246
2247 /* Allocate/fuse loword operands. */
2248 if (irref_isk((ir-1)->op2)) {
2249 leftlo = asm_fuseload(as, (ir-1)->op1, allow);
2250 } else {
2251 leftlo = ra_alloc1(as, (ir-1)->op1, allow);
2252 rset_clear(allow, leftlo);
2253 rightlo = asm_fuseload(as, (ir-1)->op2, allow);
2254 }
2255
2256 /* All register allocations must be performed _before_ this point. */
2257 l_around = emit_label(as);
2258 as->invmcp = as->flagmcp = NULL; /* Cannot use these optimizations. */
2259
2260 /* Loword comparison and branch. */
2261 asm_guardcc(as, cc >> 4); /* Always use unsigned compare for loword. */
2262 if (ra_noreg(rightlo)) {
2263 int32_t imm = IR((ir-1)->op2)->i;
2264 if (imm == 0 && ((cc >> 4) & 0xa) != 0x2 && leftlo != RID_MRM)
2265 emit_rr(as, XO_TEST, leftlo, leftlo);
2266 else
2267 emit_gmrmi(as, XG_ARITHi(XOg_CMP), leftlo, imm);
2268 } else {
2269 emit_mrm(as, XO_CMP, leftlo, rightlo);
2270 }
2271
2272 /* Hiword comparison and branches. */
2273 if ((cc & 15) != CC_NE)
2274 emit_sjcc(as, CC_NE, l_around); /* Hiword unequal: skip loword compare. */
2275 if ((cc & 15) != CC_E)
2276 asm_guardcc(as, cc >> 8); /* Hiword compare without equality check. */
2277 as->mrm = mrm; /* Restore state. */
2278 if (ra_noreg(righthi)) {
2279 int32_t imm = IR(ir->op2)->i;
2280 if (imm == 0 && (cc & 0xa) != 0x2 && lefthi != RID_MRM)
2281 emit_rr(as, XO_TEST, lefthi, lefthi);
2282 else
2283 emit_gmrmi(as, XG_ARITHi(XOg_CMP), lefthi, imm);
2284 } else {
2285 emit_mrm(as, XO_CMP, lefthi, righthi);
2286 }
2287}
2288#endif
2289
2290/* -- Support for 64 bit ops in 32 bit mode ------------------------------- */
2291
2292/* Hiword op of a split 64 bit op. Previous op must be the loword op. */
2293static void asm_hiop(ASMState *as, IRIns *ir)
2294{
2295#if LJ_32 && LJ_HASFFI
2296 /* HIOP is marked as a store because it needs its own DCE logic. */
2297 int uselo = ra_used(ir-1), usehi = ra_used(ir); /* Loword/hiword used? */
2298 if (LJ_UNLIKELY(!(as->flags & JIT_F_OPT_DCE))) uselo = usehi = 1;
2299 if ((ir-1)->o == IR_CONV) { /* Conversions to/from 64 bit. */
2300 if (usehi || uselo) {
2301 if (irt_isfp(ir->t))
2302 asm_conv_fp_int64(as, ir);
2303 else
2304 asm_conv_int64_fp(as, ir);
2305 }
2306 as->curins--; /* Always skip the CONV. */
2307 return;
2308 } else if ((ir-1)->o <= IR_NE) { /* 64 bit integer comparisons. ORDER IR. */
2309 asm_comp_int64(as, ir);
2310 return;
2311 } else if ((ir-1)->o == IR_XSTORE) {
2312 if ((ir-1)->r != RID_SINK)
2313 asm_fxstore(as, ir);
2314 return;
2315 }
2316 if (!usehi) return; /* Skip unused hiword op for all remaining ops. */
2317 switch ((ir-1)->o) {
2318 case IR_ADD:
2319 as->flagmcp = NULL;
2320 as->curins--;
2321 asm_intarith(as, ir, XOg_ADC);
2322 asm_intarith(as, ir-1, XOg_ADD);
2323 break;
2324 case IR_SUB:
2325 as->flagmcp = NULL;
2326 as->curins--;
2327 asm_intarith(as, ir, XOg_SBB);
2328 asm_intarith(as, ir-1, XOg_SUB);
2329 break;
2330 case IR_NEG: {
2331 Reg dest = ra_dest(as, ir, RSET_GPR);
2332 emit_rr(as, XO_GROUP3, XOg_NEG, dest);
2333 emit_i8(as, 0);
2334 emit_rr(as, XO_ARITHi8, XOg_ADC, dest);
2335 ra_left(as, dest, ir->op1);
2336 as->curins--;
2337 asm_neg_not(as, ir-1, XOg_NEG);
2338 break;
2339 }
2340 case IR_CALLN:
2341 case IR_CALLXS:
2342 if (!uselo)
2343 ra_allocref(as, ir->op1, RID2RSET(RID_RETLO)); /* Mark lo op as used. */
2344 break;
2345 case IR_CNEWI:
2346 /* Nothing to do here. Handled by CNEWI itself. */
2347 break;
2348 default: lua_assert(0); break;
2349 }
2350#else
2351 UNUSED(as); UNUSED(ir); lua_assert(0); /* Unused on x64 or without FFI. */
2352#endif
2353}
2354
2355/* -- Stack handling ------------------------------------------------------ */
2356
2357/* Check Lua stack size for overflow. Use exit handler as fallback. */
2358static void asm_stack_check(ASMState *as, BCReg topslot,
2359 IRIns *irp, RegSet allow, ExitNo exitno)
2360{
2361 /* Try to get an unused temp. register, otherwise spill/restore eax. */
2362 Reg pbase = irp ? irp->r : RID_BASE;
2363 Reg r = allow ? rset_pickbot(allow) : RID_EAX;
2364 emit_jcc(as, CC_B, exitstub_addr(as->J, exitno));
2365 if (allow == RSET_EMPTY) /* Restore temp. register. */
2366 emit_rmro(as, XO_MOV, r|REX_64, RID_ESP, 0);
2367 else
2368 ra_modified(as, r);
2369 emit_gri(as, XG_ARITHi(XOg_CMP), r, (int32_t)(8*topslot));
2370 if (ra_hasreg(pbase) && pbase != r)
2371 emit_rr(as, XO_ARITH(XOg_SUB), r, pbase);
2372 else
2373 emit_rmro(as, XO_ARITH(XOg_SUB), r, RID_NONE,
2374 ptr2addr(&J2G(as->J)->jit_base));
2375 emit_rmro(as, XO_MOV, r, r, offsetof(lua_State, maxstack));
2376 emit_getgl(as, r, jit_L);
2377 if (allow == RSET_EMPTY) /* Spill temp. register. */
2378 emit_rmro(as, XO_MOVto, r|REX_64, RID_ESP, 0);
2379}
2380
2381/* Restore Lua stack from on-trace state. */
2382static void asm_stack_restore(ASMState *as, SnapShot *snap)
2383{
2384 SnapEntry *map = &as->T->snapmap[snap->mapofs];
2385 SnapEntry *flinks = &as->T->snapmap[snap_nextofs(as->T, snap)-1];
2386 MSize n, nent = snap->nent;
2387 /* Store the value of all modified slots to the Lua stack. */
2388 for (n = 0; n < nent; n++) {
2389 SnapEntry sn = map[n];
2390 BCReg s = snap_slot(sn);
2391 int32_t ofs = 8*((int32_t)s-1);
2392 IRRef ref = snap_ref(sn);
2393 IRIns *ir = IR(ref);
2394 if ((sn & SNAP_NORESTORE))
2395 continue;
2396 if (irt_isnum(ir->t)) {
2397 Reg src = ra_alloc1(as, ref, RSET_FPR);
2398 emit_rmro(as, XO_MOVSDto, src, RID_BASE, ofs);
2399 } else {
2400 lua_assert(irt_ispri(ir->t) || irt_isaddr(ir->t) ||
2401 (LJ_DUALNUM && irt_isinteger(ir->t)));
2402 if (!irref_isk(ref)) {
2403 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, RID_BASE));
2404 emit_movtomro(as, REX_64IR(ir, src), RID_BASE, ofs);
2405 } else if (!irt_ispri(ir->t)) {
2406 emit_movmroi(as, RID_BASE, ofs, ir->i);
2407 }
2408 if ((sn & (SNAP_CONT|SNAP_FRAME))) {
2409 if (s != 0) /* Do not overwrite link to previous frame. */
2410 emit_movmroi(as, RID_BASE, ofs+4, (int32_t)(*flinks--));
2411 } else {
2412 if (!(LJ_64 && irt_islightud(ir->t)))
2413 emit_movmroi(as, RID_BASE, ofs+4, irt_toitype(ir->t));
2414 }
2415 }
2416 checkmclim(as);
2417 }
2418 lua_assert(map + nent == flinks);
2419}
2420
2421/* -- GC handling --------------------------------------------------------- */
2422
2423/* Check GC threshold and do one or more GC steps. */
2424static void asm_gc_check(ASMState *as)
2425{
2426 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
2427 IRRef args[2];
2428 MCLabel l_end;
2429 Reg tmp;
2430 ra_evictset(as, RSET_SCRATCH);
2431 l_end = emit_label(as);
2432 /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
2433 asm_guardcc(as, CC_NE); /* Assumes asm_snap_prep() already done. */
2434 emit_rr(as, XO_TEST, RID_RET, RID_RET);
2435 args[0] = ASMREF_TMP1; /* global_State *g */
2436 args[1] = ASMREF_TMP2; /* MSize steps */
2437 asm_gencall(as, ci, args);
2438 tmp = ra_releasetmp(as, ASMREF_TMP1);
2439 emit_loada(as, tmp, J2G(as->J));
2440 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP2), as->gcsteps);
2441 /* Jump around GC step if GC total < GC threshold. */
2442 emit_sjcc(as, CC_B, l_end);
2443 emit_opgl(as, XO_ARITH(XOg_CMP), tmp, gc.threshold);
2444 emit_getgl(as, tmp, gc.total);
2445 as->gcsteps = 0;
2446 checkmclim(as);
2447}
2448
2449/* -- Loop handling ------------------------------------------------------- */
2450
2451/* Fixup the loop branch. */
2452static void asm_loop_fixup(ASMState *as)
2453{
2454 MCode *p = as->mctop;
2455 MCode *target = as->mcp;
2456 if (as->realign) { /* Realigned loops use short jumps. */
2457 as->realign = NULL; /* Stop another retry. */
2458 lua_assert(((intptr_t)target & 15) == 0);
2459 if (as->loopinv) { /* Inverted loop branch? */
2460 p -= 5;
2461 p[0] = XI_JMP;
2462 lua_assert(target - p >= -128);
2463 p[-1] = (MCode)(target - p); /* Patch sjcc. */
2464 if (as->loopinv == 2)
2465 p[-3] = (MCode)(target - p + 2); /* Patch opt. short jp. */
2466 } else {
2467 lua_assert(target - p >= -128);
2468 p[-1] = (MCode)(int8_t)(target - p); /* Patch short jmp. */
2469 p[-2] = XI_JMPs;
2470 }
2471 } else {
2472 MCode *newloop;
2473 p[-5] = XI_JMP;
2474 if (as->loopinv) { /* Inverted loop branch? */
2475 /* asm_guardcc already inverted the jcc and patched the jmp. */
2476 p -= 5;
2477 newloop = target+4;
2478 *(int32_t *)(p-4) = (int32_t)(target - p); /* Patch jcc. */
2479 if (as->loopinv == 2) {
2480 *(int32_t *)(p-10) = (int32_t)(target - p + 6); /* Patch opt. jp. */
2481 newloop = target+8;
2482 }
2483 } else { /* Otherwise just patch jmp. */
2484 *(int32_t *)(p-4) = (int32_t)(target - p);
2485 newloop = target+3;
2486 }
2487 /* Realign small loops and shorten the loop branch. */
2488 if (newloop >= p - 128) {
2489 as->realign = newloop; /* Force a retry and remember alignment. */
2490 as->curins = as->stopins; /* Abort asm_trace now. */
2491 as->T->nins = as->orignins; /* Remove any added renames. */
2492 }
2493 }
2494}
2495
2496/* -- Head of trace ------------------------------------------------------- */
2497
2498/* Coalesce BASE register for a root trace. */
2499static void asm_head_root_base(ASMState *as)
2500{
2501 IRIns *ir = IR(REF_BASE);
2502 Reg r = ir->r;
2503 if (ra_hasreg(r)) {
2504 ra_free(as, r);
2505 if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2506 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
2507 if (r != RID_BASE)
2508 emit_rr(as, XO_MOV, r, RID_BASE);
2509 }
2510}
2511
2512/* Coalesce or reload BASE register for a side trace. */
2513static Reg asm_head_side_base(ASMState *as, IRIns *irp)
2514{
2515 IRIns *ir = IR(REF_BASE);
2516 Reg r = ir->r;
2517 if (ra_hasreg(r)) {
2518 ra_free(as, r);
2519 if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2520 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
2521 if (irp->r == r) {
2522 return r; /* Same BASE register already coalesced. */
2523 } else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
2524 emit_rr(as, XO_MOV, r, irp->r); /* Move from coalesced parent reg. */
2525 return irp->r;
2526 } else {
2527 emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
2528 }
2529 }
2530 return RID_NONE;
2531}
2532
2533/* -- Tail of trace ------------------------------------------------------- */
2534
2535/* Fixup the tail code. */
2536static void asm_tail_fixup(ASMState *as, TraceNo lnk)
2537{
2538 /* Note: don't use as->mcp swap + emit_*: emit_op overwrites more bytes. */
2539 MCode *p = as->mctop;
2540 MCode *target, *q;
2541 int32_t spadj = as->T->spadjust;
2542 if (spadj == 0) {
2543 p -= ((as->flags & JIT_F_LEA_AGU) ? 7 : 6) + (LJ_64 ? 1 : 0);
2544 } else {
2545 MCode *p1;
2546 /* Patch stack adjustment. */
2547 if (checki8(spadj)) {
2548 p -= 3;
2549 p1 = p-6;
2550 *p1 = (MCode)spadj;
2551 } else {
2552 p1 = p-9;
2553 *(int32_t *)p1 = spadj;
2554 }
2555 if ((as->flags & JIT_F_LEA_AGU)) {
2556#if LJ_64
2557 p1[-4] = 0x48;
2558#endif
2559 p1[-3] = (MCode)XI_LEA;
2560 p1[-2] = MODRM(checki8(spadj) ? XM_OFS8 : XM_OFS32, RID_ESP, RID_ESP);
2561 p1[-1] = MODRM(XM_SCALE1, RID_ESP, RID_ESP);
2562 } else {
2563#if LJ_64
2564 p1[-3] = 0x48;
2565#endif
2566 p1[-2] = (MCode)(checki8(spadj) ? XI_ARITHi8 : XI_ARITHi);
2567 p1[-1] = MODRM(XM_REG, XOg_ADD, RID_ESP);
2568 }
2569 }
2570 /* Patch exit branch. */
2571 target = lnk ? traceref(as->J, lnk)->mcode : (MCode *)lj_vm_exit_interp;
2572 *(int32_t *)(p-4) = jmprel(p, target);
2573 p[-5] = XI_JMP;
2574 /* Drop unused mcode tail. Fill with NOPs to make the prefetcher happy. */
2575 for (q = as->mctop-1; q >= p; q--)
2576 *q = XI_NOP;
2577 as->mctop = p;
2578}
2579
2580/* Prepare tail of code. */
2581static void asm_tail_prep(ASMState *as)
2582{
2583 MCode *p = as->mctop;
2584 /* Realign and leave room for backwards loop branch or exit branch. */
2585 if (as->realign) {
2586 int i = ((int)(intptr_t)as->realign) & 15;
2587 /* Fill unused mcode tail with NOPs to make the prefetcher happy. */
2588 while (i-- > 0)
2589 *--p = XI_NOP;
2590 as->mctop = p;
2591 p -= (as->loopinv ? 5 : 2); /* Space for short/near jmp. */
2592 } else {
2593 p -= 5; /* Space for exit branch (near jmp). */
2594 }
2595 if (as->loopref) {
2596 as->invmcp = as->mcp = p;
2597 } else {
2598 /* Leave room for ESP adjustment: add esp, imm or lea esp, [esp+imm] */
2599 as->mcp = p - (((as->flags & JIT_F_LEA_AGU) ? 7 : 6) + (LJ_64 ? 1 : 0));
2600 as->invmcp = NULL;
2601 }
2602}
2603
2604/* -- Instruction dispatch ------------------------------------------------ */
2605
2606/* Assemble a single instruction. */
2607static void asm_ir(ASMState *as, IRIns *ir)
2608{
2609 switch ((IROp)ir->o) {
2610 /* Miscellaneous ops. */
2611 case IR_LOOP: asm_loop(as); break;
2612 case IR_NOP: case IR_XBAR: lua_assert(!ra_used(ir)); break;
2613 case IR_USE:
2614 ra_alloc1(as, ir->op1, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR); break;
2615 case IR_PHI: asm_phi(as, ir); break;
2616 case IR_HIOP: asm_hiop(as, ir); break;
2617 case IR_GCSTEP: asm_gcstep(as, ir); break;
2618
2619 /* Guarded assertions. */
2620 case IR_LT: case IR_GE: case IR_LE: case IR_GT:
2621 case IR_ULT: case IR_UGE: case IR_ULE: case IR_UGT:
2622 case IR_EQ: case IR_NE: case IR_ABC:
2623 asm_comp(as, ir, asm_compmap[ir->o]);
2624 break;
2625
2626 case IR_RETF: asm_retf(as, ir); break;
2627
2628 /* Bit ops. */
2629 case IR_BNOT: asm_neg_not(as, ir, XOg_NOT); break;
2630 case IR_BSWAP: asm_bitswap(as, ir); break;
2631
2632 case IR_BAND: asm_intarith(as, ir, XOg_AND); break;
2633 case IR_BOR: asm_intarith(as, ir, XOg_OR); break;
2634 case IR_BXOR: asm_intarith(as, ir, XOg_XOR); break;
2635
2636 case IR_BSHL: asm_bitshift(as, ir, XOg_SHL); break;
2637 case IR_BSHR: asm_bitshift(as, ir, XOg_SHR); break;
2638 case IR_BSAR: asm_bitshift(as, ir, XOg_SAR); break;
2639 case IR_BROL: asm_bitshift(as, ir, XOg_ROL); break;
2640 case IR_BROR: asm_bitshift(as, ir, XOg_ROR); break;
2641
2642 /* Arithmetic ops. */
2643 case IR_ADD: asm_add(as, ir); break;
2644 case IR_SUB:
2645 if (irt_isnum(ir->t))
2646 asm_fparith(as, ir, XO_SUBSD);
2647 else /* Note: no need for LEA trick here. i-k is encoded as i+(-k). */
2648 asm_intarith(as, ir, XOg_SUB);
2649 break;
2650 case IR_MUL:
2651 if (irt_isnum(ir->t))
2652 asm_fparith(as, ir, XO_MULSD);
2653 else
2654 asm_intarith(as, ir, XOg_X_IMUL);
2655 break;
2656 case IR_DIV:
2657#if LJ_64 && LJ_HASFFI
2658 if (!irt_isnum(ir->t))
2659 asm_arith64(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_divi64 :
2660 IRCALL_lj_carith_divu64);
2661 else
2662#endif
2663 asm_fparith(as, ir, XO_DIVSD);
2664 break;
2665 case IR_MOD:
2666#if LJ_64 && LJ_HASFFI
2667 if (!irt_isint(ir->t))
2668 asm_arith64(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_modi64 :
2669 IRCALL_lj_carith_modu64);
2670 else
2671#endif
2672 asm_intmod(as, ir);
2673 break;
2674
2675 case IR_NEG:
2676 if (irt_isnum(ir->t))
2677 asm_fparith(as, ir, XO_XORPS);
2678 else
2679 asm_neg_not(as, ir, XOg_NEG);
2680 break;
2681 case IR_ABS: asm_fparith(as, ir, XO_ANDPS); break;
2682
2683 case IR_MIN:
2684 if (irt_isnum(ir->t))
2685 asm_fparith(as, ir, XO_MINSD);
2686 else
2687 asm_min_max(as, ir, CC_G);
2688 break;
2689 case IR_MAX:
2690 if (irt_isnum(ir->t))
2691 asm_fparith(as, ir, XO_MAXSD);
2692 else
2693 asm_min_max(as, ir, CC_L);
2694 break;
2695
2696 case IR_FPMATH: case IR_ATAN2: case IR_LDEXP:
2697 asm_fpmath(as, ir);
2698 break;
2699 case IR_POW:
2700#if LJ_64 && LJ_HASFFI
2701 if (!irt_isnum(ir->t))
2702 asm_arith64(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_powi64 :
2703 IRCALL_lj_carith_powu64);
2704 else
2705#endif
2706 asm_fppowi(as, ir);
2707 break;
2708
2709 /* Overflow-checking arithmetic ops. Note: don't use LEA here! */
2710 case IR_ADDOV: asm_intarith(as, ir, XOg_ADD); break;
2711 case IR_SUBOV: asm_intarith(as, ir, XOg_SUB); break;
2712 case IR_MULOV: asm_intarith(as, ir, XOg_X_IMUL); break;
2713
2714 /* Memory references. */
2715 case IR_AREF: asm_aref(as, ir); break;
2716 case IR_HREF: asm_href(as, ir); break;
2717 case IR_HREFK: asm_hrefk(as, ir); break;
2718 case IR_NEWREF: asm_newref(as, ir); break;
2719 case IR_UREFO: case IR_UREFC: asm_uref(as, ir); break;
2720 case IR_FREF: asm_fref(as, ir); break;
2721 case IR_STRREF: asm_strref(as, ir); break;
2722
2723 /* Loads and stores. */
2724 case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
2725 asm_ahuvload(as, ir);
2726 break;
2727 case IR_FLOAD: case IR_XLOAD: asm_fxload(as, ir); break;
2728 case IR_SLOAD: asm_sload(as, ir); break;
2729
2730 case IR_ASTORE: case IR_HSTORE: case IR_USTORE: asm_ahustore(as, ir); break;
2731 case IR_FSTORE: case IR_XSTORE: asm_fxstore(as, ir); break;
2732
2733 /* Allocations. */
2734 case IR_SNEW: case IR_XSNEW: asm_snew(as, ir); break;
2735 case IR_TNEW: asm_tnew(as, ir); break;
2736 case IR_TDUP: asm_tdup(as, ir); break;
2737 case IR_CNEW: case IR_CNEWI: asm_cnew(as, ir); break;
2738
2739 /* Write barriers. */
2740 case IR_TBAR: asm_tbar(as, ir); break;
2741 case IR_OBAR: asm_obar(as, ir); break;
2742
2743 /* Type conversions. */
2744 case IR_TOBIT: asm_tobit(as, ir); break;
2745 case IR_CONV: asm_conv(as, ir); break;
2746 case IR_TOSTR: asm_tostr(as, ir); break;
2747 case IR_STRTO: asm_strto(as, ir); break;
2748
2749 /* Calls. */
2750 case IR_CALLN: case IR_CALLL: case IR_CALLS: asm_call(as, ir); break;
2751 case IR_CALLXS: asm_callx(as, ir); break;
2752 case IR_CARG: break;
2753
2754 default:
2755 setintV(&as->J->errinfo, ir->o);
2756 lj_trace_err_info(as->J, LJ_TRERR_NYIIR);
2757 break;
2758 }
2759}
2760
2761/* -- Trace setup --------------------------------------------------------- */
2762
2763/* Ensure there are enough stack slots for call arguments. */
2764static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
2765{
2766 IRRef args[CCI_NARGS_MAX*2];
2767 int nslots;
2768 asm_collectargs(as, ir, ci, args);
2769 nslots = asm_count_call_slots(as, ci, args);
2770 if (nslots > as->evenspill) /* Leave room for args in stack slots. */
2771 as->evenspill = nslots;
2772#if LJ_64
2773 return irt_isfp(ir->t) ? REGSP_HINT(RID_FPRET) : REGSP_HINT(RID_RET);
2774#else
2775 return irt_isfp(ir->t) ? REGSP_INIT : REGSP_HINT(RID_RET);
2776#endif
2777}
2778
2779/* Target-specific setup. */
2780static void asm_setup_target(ASMState *as)
2781{
2782 asm_exitstub_setup(as, as->T->nsnap);
2783}
2784
2785/* -- Trace patching ------------------------------------------------------ */
2786
2787static const uint8_t map_op1[256] = {
27880x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x20,
27890x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,
27900x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,
27910x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,
2792#if LJ_64
27930x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,
2794#else
27950x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,
2796#endif
27970x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,
27980x51,0x51,0x92,0x92,0x10,0x10,0x12,0x11,0x45,0x86,0x52,0x93,0x51,0x51,0x51,0x51,
27990x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,
28000x93,0x86,0x93,0x93,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,
28010x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x47,0x51,0x51,0x51,0x51,0x51,
2802#if LJ_64
28030x59,0x59,0x59,0x59,0x51,0x51,0x51,0x51,0x52,0x45,0x51,0x51,0x51,0x51,0x51,0x51,
2804#else
28050x55,0x55,0x55,0x55,0x51,0x51,0x51,0x51,0x52,0x45,0x51,0x51,0x51,0x51,0x51,0x51,
2806#endif
28070x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,
28080x93,0x93,0x53,0x51,0x70,0x71,0x93,0x86,0x54,0x51,0x53,0x51,0x51,0x52,0x51,0x51,
28090x92,0x92,0x92,0x92,0x52,0x52,0x51,0x51,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,
28100x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x45,0x45,0x47,0x52,0x51,0x51,0x51,0x51,
28110x10,0x51,0x10,0x10,0x51,0x51,0x63,0x66,0x51,0x51,0x51,0x51,0x51,0x51,0x92,0x92
2812};
2813
2814static const uint8_t map_op2[256] = {
28150x93,0x93,0x93,0x93,0x52,0x52,0x52,0x52,0x52,0x52,0x51,0x52,0x51,0x93,0x52,0x94,
28160x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
28170x53,0x53,0x53,0x53,0x53,0x53,0x53,0x53,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
28180x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x34,0x51,0x35,0x51,0x51,0x51,0x51,0x51,
28190x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
28200x53,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
28210x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
28220x94,0x54,0x54,0x54,0x93,0x93,0x93,0x52,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
28230x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,
28240x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
28250x52,0x52,0x52,0x93,0x94,0x93,0x51,0x51,0x52,0x52,0x52,0x93,0x94,0x93,0x93,0x93,
28260x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x94,0x93,0x93,0x93,0x93,0x93,
28270x93,0x93,0x94,0x93,0x94,0x94,0x94,0x93,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,
28280x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
28290x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
28300x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x52
2831};
2832
2833static uint32_t asm_x86_inslen(const uint8_t* p)
2834{
2835 uint32_t result = 0;
2836 uint32_t prefixes = 0;
2837 uint32_t x = map_op1[*p];
2838 for (;;) {
2839 switch (x >> 4) {
2840 case 0: return result + x + (prefixes & 4);
2841 case 1: prefixes |= x; x = map_op1[*++p]; result++; break;
2842 case 2: x = map_op2[*++p]; break;
2843 case 3: p++; goto mrm;
2844 case 4: result -= (prefixes & 2); /* fallthrough */
2845 case 5: return result + (x & 15);
2846 case 6: /* Group 3. */
2847 if (p[1] & 0x38) x = 2;
2848 else if ((prefixes & 2) && (x == 0x66)) x = 4;
2849 goto mrm;
2850 case 7: /* VEX c4/c5. */
2851 if (LJ_32 && p[1] < 0xc0) {
2852 x = 2;
2853 goto mrm;
2854 }
2855 if (x == 0x70) {
2856 x = *++p & 0x1f;
2857 result++;
2858 if (x >= 2) {
2859 p += 2;
2860 result += 2;
2861 goto mrm;
2862 }
2863 }
2864 p++;
2865 result++;
2866 x = map_op2[*++p];
2867 break;
2868 case 8: result -= (prefixes & 2); /* fallthrough */
2869 case 9: mrm: /* ModR/M and possibly SIB. */
2870 result += (x & 15);
2871 x = *++p;
2872 switch (x >> 6) {
2873 case 0: if ((x & 7) == 5) return result + 4; break;
2874 case 1: result++; break;
2875 case 2: result += 4; break;
2876 case 3: return result;
2877 }
2878 if ((x & 7) == 4) {
2879 result++;
2880 if (x < 0x40 && (p[1] & 7) == 5) result += 4;
2881 }
2882 return result;
2883 }
2884 }
2885}
2886
2887/* Patch exit jumps of existing machine code to a new target. */
2888void lj_asm_patchexit(jit_State *J, GCtrace *T, ExitNo exitno, MCode *target)
2889{
2890 MCode *p = T->mcode;
2891 MCode *mcarea = lj_mcode_patch(J, p, 0);
2892 MSize len = T->szmcode;
2893 MCode *px = exitstub_addr(J, exitno) - 6;
2894 MCode *pe = p+len-6;
2895 MCode *pgc = NULL;
2896 uint32_t stateaddr = u32ptr(&J2G(J)->vmstate);
2897 if (len > 5 && p[len-5] == XI_JMP && p+len-6 + *(int32_t *)(p+len-4) == px)
2898 *(int32_t *)(p+len-4) = jmprel(p+len, target);
2899 /* Do not patch parent exit for a stack check. Skip beyond vmstate update. */
2900 for (; p < pe; p += asm_x86_inslen(p))
2901 if (*(uint32_t *)(p+(LJ_64 ? 3 : 2)) == stateaddr && p[0] == XI_MOVmi)
2902 break;
2903 lua_assert(p < pe);
2904 for (; p < pe; p += asm_x86_inslen(p)) {
2905 if ((*(uint16_t *)p & 0xf0ff) == 0x800f && p + *(int32_t *)(p+2) == px &&
2906 p != pgc) {
2907 *(int32_t *)(p+2) = jmprel(p+6, target);
2908 } else if (*p == XI_CALL &&
2909 (void *)(p+5+*(int32_t *)(p+1)) == (void *)lj_gc_step_jit) {
2910 pgc = p+7; /* Do not patch GC check exit. */
2911 }
2912 }
2913 lj_mcode_sync(T->mcode, T->mcode + T->szmcode);
2914 lj_mcode_patch(J, mcarea, 1);
2915}
2916